1. A thermosetting adhesive and pressure-sensitive adhesive composition comprising 100 parts by weight of an acrylic polymer (X) containing, as monomer components, a (meth)acrylic acid alkyl ester (a) where the alkyl group has 2 to 14 carbon atoms in an amount of 60 to 75% by weight relative to the total amount of monomer components, a cyano group-containing monomer (b) in an amount of 20 to 35% by weight relative to the total amount of monomer components, and a carboxyl group-containing monomer (c) in an amount of 0.5 to 10% by weight relative to the total amount of monomer components and 1 to 20 parts by weight of a carbolic acid-based resorcinol-type phenol resin (Y) represented by the following formula (1):
wherein R1 represents \u2014CH2\u2014 or \u2014CH2\u2014O\u2014CH2\u2014, n is a positive integer, and m is an integer of 1 to 4,
and further comprising an ultraviolet absorbent (Z).
2. The thermosetting adhesive and pressure-sensitive adhesive composition according to claim 1, wherein the ultraviolet absorbent (Z) contains a nitrogen atom in the molecule.
3. The thermosetting adhesive and pressure-sensitive adhesive composition according to claim 1, wherein the ratio of the ultraviolet absorbent (Z) is from 1 to 20 parts by weight relative to 100 parts by weight of the acrylic polymer (X).
4. A thermosetting adhesive and pressure-sensitive adhesive tape or sheet having a thermosetting adhesive and pressure-sensitive adhesive layer formed of the thermosetting adhesive and pressure-sensitive adhesive composition according to claim 1.
5. The thermosetting adhesive and pressure-sensitive adhesive tape or sheet according to claim 4, wherein storage modulus at 23\xb0 C. of the thermosetting adhesive and pressure-sensitive adhesive layer is from 1\xd7106 to 1\xd7108 Pa.
6. A wiring circuit board at least comprising an electric insulating layer and an electric conductor formed on the electric insulator layer so as to form a predetermined circuit pattern, which comprises an adhesive layer formed by thermal hardening of the thermosetting adhesive and pressure-sensitive adhesive composition according to claim 1.
7. The wiring circuit board according to claim 6, which has the adhesive layer formed by thermal hardening of the above thermosetting adhesive and pressure-sensitive adhesive composition at least one site among sites between the electric insulator layer and the electric conductor layer, between the electric conductor layer and a covering electric insulator layer provided on the electric conductor layer, and between the electric insulator layer and a reinforcing plate provided on the surface of the electric insulator layer opposite to the electric conductor layer.
8. The wiring circuit board according to claim 6, wherein the wiring circuit board has a multilayer structure where a plurality of wiring circuit boards are laminated and has the adhesive layer formed by thermal hardening of the above thermosetting adhesive and pressure-sensitive adhesive composition between one set or two or more sets of the wiring circuit boards.
9. The wiring circuit board according to claim 6, wherein the adhesive layer formed by thermal hardening of the above thermosetting adhesive and pressure-sensitive adhesive composition is formed using a thermosetting adhesive and pressure-sensitive adhesive tape or sheet having a constitution that it is formed of only a thermosetting adhesive and pressure-sensitive adhesive layer derived from the above thermosetting adhesive and pressure-sensitive adhesive composition.
10. The wiring circuit board according to claim 9, wherein the adhesive layer formed by thermal hardening of the above thermosetting adhesive and pressure-sensitive adhesive composition is formed by attaching predetermined members to both sides of the thermosetting adhesive and pressure-sensitive adhesive tape or sheet, followed by thermal hardening upon heating under pressure.
11. The wiring circuit board according to claim 6, wherein thickness of the adhesive layer formed by thermal hardening of the above thermosetting adhesive and pressure-sensitive adhesive composition is from 3 to 100 \u03bcm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor device comprising:
a first transistor having a gate insulating film of a first thickness, at least one of sourcedrain of said first transistor being formed of a first lightly doped region and a first heavily doped region; and
a second transistor having a gate insulating film of a second thickness smaller than said first thickness, at least one of sourcedrain of said second transistor including a second lightly doped region and a second heavily doped region higher in concentration than said first heavily doped region.
2. The semiconductor device according to claim 1, wherein
at least one of the sourcedrain of said second transistor has a medium-doped region having a concentration higher than said second lightly doped region and lower than said second heavily doped region.
3. The semiconductor device according to claim 1, wherein
said semiconductor device includes a memory cell portion for storing data and a peripheral circuit portion for external inputoutput,
said memory cell portion includes said first transistor, and
said peripheral circuit portion includes said second transistor.
4. The semiconductor device according to claim 2, wherein
a diffusion depth of said second heavily doped region is smaller than a diffusion depth of said medium-doped region.
5. The semiconductor device according to claim 1, wherein
a field insulating film is formed in contact with said first heavily doped region,
said first and second transistors are covered with an interlayer insulating film having a contact hole reaching said first heavily doped region and said field insulating film, and
a concavity is formed at said field insulating film located immediately under said contact hole, and
a storage node is formed in said concavity and on said first heavily doped region.
6. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a first impurity region for threshold voltage control having a peak concentration at a position of a first depth from said main surface;
a second impurity region for threshold voltage control spaced from said first impurity region, and having a peak concentration at a position of a second depth larger than said first depth;
a first transistor formed on said first impurity region, and having a gate insulating film of a first thickness; and
a second transistor formed on said second impurity region, and having a gate insulating film of a second thickness smaller than said first thickness;
7. The semiconductor device according to claim 6, wherein
a third impurity region lower in concentration than said first impurity region is formed under said first impurity region,
said first transistor has a pair of first sourcedrain,
at least one of said first sourcedrain reaches said third impurity region,
said second transistor has a pair of second sourcedrain, and
said second sourcedrain have diffusion depths smaller than said second depth.
8. A semiconductor device comprising:
a first transistor having a gate insulating film of a first thickness, and having first and second impurity regions having relatively large first diffusion depth and relatively small second diffusion depth and forming sourcedrain, respectively, and;
a second transistor having a gate insulating film of a second thickness smaller than said first thickness, and having third and fourth diffusion regions having diffusion depths smaller than said first diffusion depth and not smaller than said second diffusion depth, and forming sourcedrain, respectively.
9. The semiconductor device according to claim 8, wherein
a concentration of said first impurity region having said first diffusion depth is higher than a concentration of said second impurity region, and a field insulating film is formed in contact with said first impurity region.
10. A semiconductor device comprising:
a first transistor formed on a main surface of a semiconductor substrate, and having first sourcedrain;
a second transistor formed on said main surface with a space from said first transistor, and having second sourcedrain;
an interlayer insulating film covering said first and second transistors, and having a contact hole reaching one of said first sourcedrain;
a plug electrode formed in said contact hole;
first metal silicide formed on surfaces of said second sourcedrain; and
a bit line formed on said plug electrode with a second metal silicide therebetween.