1. A map information processing apparatus comprising:
a position detecting means for detecting a position thereof;
a map information storage unit for storing map information including road information;
a new road detecting unit for, when information about a road corresponding to the position detected by said position detecting means does not exist in the road information acquired from said map information storage unit, detecting, as a new road, said road, and generating new road running history information showing a history of running along said detected new road;
a new road generating unit for generating new road information on a basis of the new road running history information generated by said new road detecting unit;
a new road information storage unit for storing the new road information generated by said new road generating unit;
a new road editing unit for editing new road information acquired from said new road information storage unit; and
a road information updating unit for updating the road information by adding the new road information edited by said new road editing unit to said map information storage unit.
2. The map information processing apparatus according to claim 1, characterized in that said map information processing apparatus includes: a reference-point-to-be-moved specifying means for specifying a reference point which is an object to be moved from among reference points which define the new road shown by the new road information acquired from the new road information storage unit; and a reference-point-to-be-moved coordinate specifying means for specifying point coordinates of a movement destination of the reference point specified by said reference-point-to-be-moved specifying means, and characterized in that the new road editing unit moves the reference point specified by said reference-point-to-be-moved specifying means to a position at the point coordinates specified by said reference-point-to-be-moved coordinate specifying means.
3. The map information processing apparatus according to claim 2, characterized in that the reference point specified by the reference-point-to-be-moved specifying means is a start point or an end point of the new road shown by the new road information.
4. The map information processing apparatus according to claim 2, characterized in that when judging that an existing road exists in a vicinity of the point coordinates specified by the reference-point-to-be-moved coordinate specifying means, the new road editing unit converts the point coordinates specified by said reference-point-to-be-moved coordinate specifying means into point coordinates of a reference point on the existing road in a vicinity of a point shown by said point coordinates.
5. The map information processing apparatus according to claim 2, characterized in that when judging that there is an intersection in a vicinity of the point coordinates specified by the reference-point-to-be-moved coordinate specifying means, the new road editing unit converts the point coordinates specified by said reference-point-to-be-moved coordinate specifying means into point coordinates at said intersection.
6. The map information processing apparatus according to claim 2, characterized in that said map information processing apparatus includes a running history storage unit for storing a running history, the new road editing unit estimates candidates for the reference point which is the object to be moved on a basis of the running history stored in said running history storage unit, and said reference-point-to-be-moved specifying means specifies the reference point which is the object to be moved from among said estimated candidates for the reference point.
7. The map information processing apparatus according to claim 2, characterized in that said map information processing apparatus includes a running history storage unit for storing a running history, the new road editing unit estimates candidates for the point coordinates which are the movement destination on a basis of the running history stored in said running history storage unit, and said reference-point-to-be-moved coordinate specifying means specifies the point coordinates of the reference point specified by the reference-point-to-be-moved specifying means from among said estimated candidates for the point coordinates.
8. The map information processing apparatus according to claim 1, characterized in that said map information processing apparatus includes an additional reference point specifying means for specifying a point to be added newly as a reference point which defines the new road shown by the new road information acquired from the new road information storage unit, and the new road editing unit generates the new road information including the reference point specified by said additional reference point specifying means.
9. The map information processing apparatus according to claim 8, characterized in that said map information processing apparatus includes a reference-point-to-be-connected specifying means for specifying another reference point which is to be connected to the reference point newly added through the specification by the additional reference point specifying means, and the new road editing unit generates the new road information including both the reference point specified by said additional reference point specifying means and the other reference point specified by said connected reference point specifying means.
10. The map information processing apparatus according to claim 1, characterized in that said map information processing apparatus includes a reference-point-to-be-deleted specifying means for specifying a reference point which is to be deleted from among the plurality of reference points which define the new road shown by the new road information acquired from the new road information storage unit, and the new road editing unit generates the new road information excluding the reference point which is deleted by said reference-point-to-be-deleted specifying means.
11. The map information processing apparatus according to claim 10, characterized in that the reference-point-to-be-deleted specifying means specifies a part of segments connecting the plurality of reference points which define the new road shown by the new road information acquired from the new road information storage unit so as to specify a reference point included in said segments as an object to be deleted.
12. The map information processing apparatus according to claim 10, characterized in that the reference-point-to-be-deleted specifying means specifies an area surrounding the plurality of reference points which define the new road shown by the new road information acquired from the new road information storage unit so as to specify a reference point included in said area as an object to be deleted.
13. The map information processing apparatus according to claim 8, characterized in that when judging that an existing road exists in a vicinity of the point coordinates specified by the additional reference point specifying means, the new road editing unit converts the point coordinates specified by said additional reference point specifying means into point coordinates of a reference point on the existing road which is nearest to a point shown by said specified point coordinates.
14. The map information processing apparatus according to claim 13, characterized in that said map information processing apparatus includes a user inquiring means for inquiring of a user whether or not the point coordinates specified by the additional reference point specifying means are those of a point on an existing road, and, when judging that an existing road exists in a vicinity of the point coordinates specified by said additional reference point specifying means and said user inquiring means has recognized that the point coordinates specified by the additional reference point specifying means are those of a point on an existing road, the new road editing unit converts the point coordinates specified by said additional reference point specifying means into point coordinates of a reference point on said recognized existing road.
15. The map information processing apparatus according to claim 8, characterized in that when judging that there is an intersection in a vicinity of the point coordinates specified by the additional reference point specifying means, the new road editing unit converts the point coordinates specified by said additional reference point specifying means into point coordinates at said intersection.
16. The map information processing apparatus according to claim 15, characterized in that said map information processing apparatus includes a user inquiring means for inquiring of a user whether or not the point coordinates specified by the additional reference point specifying means are those of an intersection, and, when judging that there is an intersection in a vicinity of the point coordinates specified by the additional reference point specifying means and said user inquiring means has recognized that the point coordinates specified by the additional reference point specifying means are those of an intersection, the new road editing unit converts the point coordinates specified by said additional reference point specifying means into point coordinates at said intersection.
17. The map information processing apparatus according to claim 13, characterized in that said map information processing apparatus includes a user inquiring means for, when a plurality of existing roads exist in a vicinity of the point coordinates specified by the additional reference point specifying means, inquiring of a user about road attributes of the plurality of existing roads, and the new road editing unit converts the point coordinates specified by said additional reference point specifying means into point coordinates of a reference point on an existing road having a road attribute recognized by said user inquiring means.
18. The map information processing apparatus according to claim 1, characterized in that the new road editing unit estimates a shape of the new road on a basis of the edited new road information, and the road information updating unit updates the road information by adding the new road information about the new road having the shape estimated by said new road editing unit to the map information storage unit.
19. The map information processing apparatus according to claim 18, characterized in that said map information processing apparatus includes a user inquiring means for inquiring of a user about validity of the shape of the new road estimated by the new road editing unit, and, when said user inquiring means has recognized that the shape of the new road has validity, the road information updating unit updates the road information by adding the new road information about the new road having the shape estimated by the new road editing unit to the map information storage unit.
20. The map information processing apparatus according to claim 18, characterized in that said map information processing apparatus includes a shape selecting means for selecting one shape from a plurality of shapes of the new road which are estimated by the new road editing unit, and the road information updating unit updates the road information by adding the new road information about the new road having the shape selected by the shape selecting means to the map information storage unit.
21. The map information processing apparatus according to claim 1, characterized in that when moving a new road through editing, the new road editing unit corrects the new road information about the new road on a basis of the position information detected by the position detecting means.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for manufacturing an integrated circuit ferroelectric memory device, comprising the steps of:
forming a first patterned conductive layer on an integrated circuit substrate to define a lower capacitor electrode and a gate electrode that is spaced apart therefrom;
forming a source region and a drain region on opposite sides of the gate electrode;
forming a ferroelectric layer on the lower capacitor electrode; and
forming an upper capacitor electrode on the ferroelectric layer opposite the lower capacitor electrode, to thereby form a ferroelectric capacitor.
2. A method according to claim 1 wherein the step of forming a source region and a drain region precedes the step of forming a first patterned conductive layer, such that the gate electrode is formed between the source region and drain region.
3. A method according to claim 1 wherein the lower capacitor electrode includes a lower capacitor electrode sidewall, wherein the gate electrode includes a gate electrode sidewall and wherein the following step is performed between the steps of forming a first patterned conductive layer and forming a source region and a drain region:
forming a lower capacitor electrode sidewall spacer and a gate electrode sidewall spacer on the lower capacitor electrode sidewall and on the gate electrode sidewall, respectively.
4. A method according to claim 1 wherein the following step is performed between the steps of forming a ferroelectric layer and forming an upper capacitor electrode:
forming an interlayer dielectric layer on the gate electrode that exposes the lower electrode.
5. A method according to claim 1 wherein the step of forming a first patterned conductive layer comprises the steps of:
forming an insulating layer on the integrated circuit substrate;
forming a conductive layer on the insulating layer opposite the integrated circuit substrate; and
patterning the conductive layer and the insulating layer to form the first patterned conductive layer.
6. A method according to claim 5 wherein the step of forming a conductive layer comprises the steps of:
forming a first conductive sublayer on the insulating layer; and
forming a second conductive sublayer on the first conductive sublayer; and
wherein the step of patterning the conductive layer and the insulating layer comprises the step of patterning the second conductive sublayer, the first conductive sublayer and the insulating layer.
7. A method according to claim 1:
wherein the step of forming a first patterned conductor layer comprises the step of forming a first patterned conductive layer on an integrated circuit substrate to define a lower capacitor electrode and a pair of gate electrodes that are spaced apart from one another; and
wherein the step of forming a source region and a drain region comprises the step of forming a drain region between the spaced apart gate electrodes and forming a pair of source regions outside the gate electrodes, on opposite sides thereof.
8. A method according to claim 4 wherein the step of forming a ferroelectric layer comprises the steps of:
forming a ferroelectric layer on the interlayer dielectric layer and on the exposed lower electrode; and
removing the ferroelectric layer from on the interlayer dielectric layer so that the ferroelectric layer only remains on the exposed lower electrode.
9. A method according to claim 8 wherein the removing step comprises the step of chemical-mechanical polishing the ferroelectric layer.
10. A method according to claim 4 wherein the interlayer dielectric layer includes a sidewall on the lower electrode, and wherein the following step is performed prior to the step of forming a ferroelectric layer:
forming a sidewall spacer on the dielectric layer sidewall, to reduce diffusion from the ferroelectric layer.
11. A method according to claim 1 wherein the step of forming an upper capacitor electrode is followed by the steps of:
forming a second patterned conductive layer on the source and drain regions and on the top electrode, to define an interconnect layer that electrically connects the top electrode and the source region, and a bit line that electrically contacts the drain region.
12. A method according to claim 1 1 wherein the step of forming a second patterned conductive layer is preceded by the step of forming a second interlayer dielectric layer on the source and drain regions and on the upper electrode, the second interlayer dielectric layer exposing a portion of the source region, the drain region and the upper electrode.
13. A method according to claim 12 wherein the step of forming a second interlayer dielectric layer is followed by the step of forming a capping layer on the upper electrode, to reduce diffusion from the ferroelectric layer through the upper electrode.
14. A method for manufacturing an integrated circuit ferroelectric memory device, comprising the steps of:
forming a first patterned conductive layer on an integrated circuit substrate to define a lower capacitor electrode and a gate electrode that is spaced apart therefrom;
forming a source region and a drain region on opposite sides of the gate electrode;
forming an unpatterned ferroelectric layer on the lower capacitor electrode, the gate electrode and the source and drain regions;
forming an unpatterned upper capacitor electrode layer on the ferroelectric layer; and
patterning the unpatterned upper capacitor layer and the unpatterned ferroelectric layer, to thereby form a patterned ferroelectric layer and a patterned upper electrode of a ferroelectric capacitor.
15. A method according to claim 14 wherein the step of forming a source region and a drain region precedes the step of forming a first patterned conductive layer, such that the gate electrode is formed between the source region and drain region.
16. A method according to claim 14 wherein the lower capacitor electrode includes a lower capacitor electrode sidewall, wherein the gate electrode includes a gate electrode sidewall and wherein the following step is performed between the steps of forming a first patterned conductive layer and forming a source region and a drain region:
forming a lower capacitor electrode sidewall spacer and a gate electrode sidewall spacer on the lower capacitor electrode sidewall and on the gate electrode sidewall, respectively.
17. A method according to claim 14 wherein the following step is performed prior to the step of forming an unpatterned ferroelectric layer:
forming an interlayer dielectric layer on the gate electrode and the source and drain regions, that exposes the lower electrode; and
wherein the step of forming an unpatterned ferroelectric layer comprises the step of forming an unpatterned ferroelectric layer on the exposed lower capacitor electrode and on the interlayer dielectric layer.
18. A method according to claim 14 wherein the step of forming a first patterned conductive layer comprises the steps of:
forming an insulating layer on the integrated circuit substrate;
forming a conductive layer on the insulating layer opposite the integrated circuit substrate; and
patterning the conductive layer and the insulating layer to form the first patterned conductive layer.
19. A method according to claim 18 wherein the step of forming a conductive layer comprises the steps of:
forming a first conductive sublayer on the insulating layer; and
forming a second conductive sublayer on the first conductive sublayer; and
wherein the step of patterning the conductive layer and the insulating layer comprises the step of patterning the second conductive sublayer, the first conductive sublayer and the insulating layer.
20. A method according to claim 14:
wherein the step of forming a first patterned conductor layer comprises the step of forming a first patterned conductive layer on an integrated circuit substrate to define a lower capacitor electrode and a pair of gate electrodes that are spaced apart from one another; and
wherein the step of forming a source region and a drain region comprises the step of forming a drain region between the spaced apart gate electrodes and forming a pair of source regions outside the gate electrodes, on opposite sides thereof.
21. A method according to claim 14 wherein the step of patterning is followed by the step of:
forming a second patterned conductive layer on the source and drain regions and on the top electrode, to define an interconnect layer that electrically connects the top electrode and the source region, and a bit line that electrically contacts the drain region.
22. A method according to claim 21 wherein the step of forming a second patterned conductive layer is preceded by the step of forming a second interlayer dielectric layer on the source and drain regions and on the upper electrode, the second interlayer dielectric layer exposing a portion of the source region, the drain region and the upper electrode.
23. A method according to claim 22 wherein the step of forming a second interlayer dielectric layer is followed by the step of forming a capping layer on the upper electrode, to reduce diffusion from the ferroelectric layer through the upper electrode.
24. A method for manufacturing an integrated circuit ferroelectric memory device, comprising the steps of:
forming a lower capacitor electrode and a gate electrode that is spaced apart therefrom on an integrated circuit substrate, and a source region and a drain region on opposite sides of the gate electrode;
forming a ferroelectric layer on the lower capacitor electrode;
forming an upper capacitor electrode on the ferroelectric layer opposite the lower capacitor electrode, to thereby form a ferroelectric capacitor; and
forming a patterned conductive layer on the source and drain regions and the top electrode, to define an interconnect layer that electrically connects the top electrode and the source region, and a bit line that electrically contacts the drain region.
25. A method according to claim 24 wherein the step of forming a patterned conductive layer is preceded by the step of forming an interlayer dielectric layer on the source and drain regions and on the upper electrode, the interlayer dielectric layer exposing a portion of the source region, the drain region and the upper electrode.
26. A method according to claim 25 wherein the step of forming an interlayer dielectric layer is followed by the step of forming a capping layer on the upper electrode, to reduce diffusion from the ferroelectric layer through the upper electrode.
27. An integrated circuit ferroelectric memory device comprising:
an integrated circuit substrate including an elongated active region therein;
a pair of spaced apart word lines that cross the elongated active region;
a drain region in the elongated active region between the pair of word lines;
a pair of source regions in the elongated active region, a respective one of which is outside the pair of spaced apart word lines on opposite sides of the drain region;
a pair of ferroelectric capacitors outside the elongated active region, a respective one of which is adjacent a respective one of the pair of source regions, each of the ferroelectric capacitors comprising:
a lower electrode on the integrated circuit substrate and extending along the integrated circuit substrate parallel to the word lines to define a plate line;
a ferroelectric layer on the lower electrode opposite the integrated circuit substrate; and
an upper electrode on the ferroelectric layer opposite the lower electrode;
an interconnect layer that electrically connects a respective one of the upper electrodes to a respective one of the source regions; and
a bit line, electrically connected to the drain region and extending along the integrated circuit substrate orthogonal to the word lines.
28. An integrated circuit ferroelectric memory device according to claim 27 further comprising a first conductive layer, and wherein the pair of spaced apart word lines and the lower electrodes comprise first and second portions, respectively, of the first conductive layer.
29. An integrated circuit ferroelectric memory device according to claim 28 wherein the first conductive layer comprises a first sublayer comprising doped polysilicon and a second sublayer on the first sublayer, the second sublayer comprising at least one of platinum, iridium, ruthenium, tungsten, iridium oxide, rhenium oxide, and ruthenium oxide.
30. An integrated circuit ferroelectric memory device according to claim 27 wherein the ferroelectric layer includes a sidewall, the integrated circuit memory device further comprising a sidewall spacer on the sidewall.
31. An integrated circuit ferroelectric memory device according to claim 30 wherein the sidewall spacer comprises aluminum oxide.
32. An integrated circuit ferroelectric memory device according to claim 27 wherein the ferroelectric layer comprises at least one of PZT, PLZT and Yi.
33. An integrated circuit ferroelectric memory device according to claim 29 wherein the upper electrode comprises same material as the second sublayer.
34. An integrated circuit ferroelectric memory device according to claim 27 further comprising a second conductive layer, and wherein the interconnect layer and the bit line comprise first and second portions, respectively, of the second conductive layer.
35. An integrated circuit ferroelectric memory device according to claim 34 wherein the second conductive layer comprises at least one of doped polysilicon, tungsten and aluminum.
36. An integrated circuit ferroelectric memory device according to claim 27 further comprising a capping layer on the upper electrode opposite the ferroelectric layer that reduces diffusion from the ferroelectric layer through the upper electrode.
37. An integrated circuit ferroelectric memory device according to claim 36 wherein the capping layer comprises titanium oxide.