1. A cover for an energy guide chain, wherein the cover comprises:
a first end region;
a second end region; and
an elastic section between the first end region and the second end region; wherein the cover has an initial length and a second length when subjected to tension to define an actual length change S, and wherein the following ratio applies:
\u0394LS<1
where \u0394L is a length change of the cover with a length L0 due to a force according to Hooke’s law, and S is the actual length change of the cover due to the force.
2. The cover according to claim 1, wherein the elastic section has a wavy shape.
3. The cover according to claim 2, wherein the elastic section has waves of different heights.
4. The cover according to claim 2, wherein the elastic section has waves of different periods.
5. The cover according to claim 2, wherein elastic section wavy shape comprises a first wave and a second wave, each wave having flanks of a different slope than the other wave.
6. The cover according to claim 2, wherein the wavy shape defines a first wave and a second wave, each wave comprising a wave trough and a wave crest, and a curvature of the wave trough and wave crest of the first wave is different than the curvature of the wave trough and wave crest of the second wave.
7. The cover according to claim 5, wherein each wave further comprises a wave crest, and the first wave crest has a different cross-section than the flank of the first wave.
8. The cover according to claim 7, wherein the first wave crest has a thickness that is less than the thickness of the flank of the first wave.
9. The cover according to claim 2, wherein the wavy section further comprises:
a localized reinforcing microstructure.
10. The cover according to claim 2, wherein the elastic section has a first region and a second region, and wherein a structure of the first region is different than the structure of the second region.
11. The cover according to claim 1, and further comprising:
a first cover part;
a second cover part partially overlapping the first cover part; and
a transverse plate linked to the first and second cover parts.
12. The cover according to claim 11, wherein the plate is made at least partially of an elastic material.
13. The cover according to claim 11, wherein a portion of the plate has a wavy shape.
14. The cover according to claim 1, wherein the first end region comprises a lock for engagement with a transverse link of a chain link.
15. The cover according to claim 1, wherein the first end region is a transverse link in a chain.
16. The cover according to claim 1, and further comprising:
a plurality of cover sections and a fastening region formed between two cover sections for linking the cover to a chain link.
17. The cover according to claim 1, wherein the cover is made at least partially of plastic.
18. The cover according to claim 1, wherein the cover is made of at least two plastics with different elasticities.
19. A chain link of an energy guide chain comprising:
two mounting links;
a transverse link joining the mounting links;
and a cover comprising:
a first end region and a second end region and an elastic section disposed between the first end region and the second end region, and wherein the cover satisfies the following relationship when a force is applied to the cover:
\u0394LS<1
where \u0394L is the length change of the cover with a length L0 according to Hooke’s law, and S is the actual length change of the cover when force is applied to the cover.
20. The chain link according to claim 19, wherein the cover is separably joined to the transverse link.
21. The chain link according to claim 20, wherein the transverse link is joined pivotably to a mounting link.
22. The chain link according to claim 19, and further comprising:
a fastening element joined to the cover.
23. The chain link according to claim 19, and further comprising a second traverse link, and wherein the cover extends between the transverse links.
24. The energy guide chain according to claim 23, and wherein the cover is connected to the traverse link.
25. An energy guide chain comprising:
a plurality of chain links;
a joint linking adjacent chain links; and
a cover joined to at least one chain link;
wherein the cover comprises:
a first end region;
a second end region; and
an elastic section disposed between the first end region and second end region, such that the following relationship applies to the cover:
\u0394LS<1
where \u0394L is the length change of the cover with a length L0 according to Hooke’s law, and S is the actual length change of the cover when force is applied to the cover.
26. The energy guide chain according to claim 25, wherein the cover extends over at least two chain links.
27. The energy guide chain according to claim 25, and further comprising:
a traverse link; and
wherein the first end region is separably connected with the transverse link.
28. The energy guide chain according to claim 25, and further comprising:
cover fastening elements joined to a chain link.
29. The energy guide chain according to claim 25, wherein the cover is joined to two neighboring chain links.
30. The energy guide chain according to claim 27, and further comprising a second traverse link, and wherein the cover extends between the transverse links.
31. The energy guide chain according to claim 30, and wherein the cover is connected to the traverse link.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of providing a reference voltage in an integrated circuit, comprising:
programming a threshold voltage of a first non-volatile memory (NVM) transistor via a tunneling capacitor, wherein the first NVM transistor and the tunneling capacitor share a first floating gate and the tunneling capacitor has a programming terminal separate from the first floating gate; then
coupling the programming terminal of the tunneling capacitor to a semiconductor structure having electrical and thermal characteristics selected to match electrical and thermal characteristics of the first floating gate; and
generating a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor while the programming terminal of the tunneling capacitor is coupled to the semiconductor structure.
2. The method of claim 1, wherein the step of programming the threshold voltage of the first NVM transistor comprises applying a programming voltage across the programming terminal of the tunneling capacitor and the first floating gate.
3. The method of claim 1, further comprising:
coupling a second NVM transistor in a current mirror configuration with the first NVM transistor during the step of programming the threshold voltage of the first NVM transistor; and
applying a reference voltage to the second NVM transistor during the step of programming the threshold voltage of the first NVM transistor.
4. The method of claim 3, further comprising:
coupling the first NVM transistor and the second NVM transistor to a differential amplifier during the step of programming the threshold voltage of the first NVM transistor; and
terminating the step of programming the threshold voltage of the first NVM transistor when an output of the differential amplifier switches.
5. The method of claim 3, further comprising initializing a threshold voltage of the second NVM transistor to a neutral state prior to programming the threshold voltage of the first NVM transistor.
6. The method of claim 5, wherein the step of initializing the threshold voltage of the second NVM transistor comprises exposing the second NVM transistor to ultra-violet (UV) radiation.
7. The method of claim 1, further comprising coupling a second NVM transistor in a current mirror configuration with the first NVM transistor during the step of generating the single-ended reference voltage.
8. The method of claim 7, further comprising coupling the first NVM transistor and the second NVM transistor to inputs of a differential amplifier during the step of generating the single-ended reference voltage, wherein the differential amplifier provides the single-ended reference voltage.
9. The method of claim 7, wherein a first current flows through the first NVM transistor during the step of generating the single-ended reference voltage, the method further comprising causing a current equal to the first current to flow through the semiconductor structure during the step of generating the single-ended reference voltage.
10. The method of claim 1, further comprising erasing the first NVM transistor via the tunneling capacitor prior to programming the threshold voltage of the first NVM transistor.
11. The method of claim 1, wherein the threshold voltage of the first NVM transistor is programmed by Fowler-Nordheim tunneling.
12. A voltage reference circuit for generating a reference voltage, comprising:
a first non-volatile memory (NVM) transistor having a first floating gate configured to store a programmed charge, wherein the reference voltage is generated in response to the programmed charge stored on the first floating gate;
a tunneling capacitor that shares the first floating gate with the first NVM transistor, wherein the tunneling capacitor has a programming terminal separate from the first floating gate;
a semiconductor structure having electrical and thermal characteristics selected to match electrical and thermal characteristics of the first NVM transistor;
a first switch configured to couple the programming terminal to the semiconductor structure during a normal operating mode in which the voltage reference circuit generates the reference voltage.
13. The voltage reference circuit of claim 12, further comprising a second switch configured to couple the programming terminal to a programming voltage during a programming mode in which the programmed charge is stored on the first floating gate.
14. The voltage reference circuit of claim 12, wherein the programming terminal comprises commonly coupled sourcedrain regions of a non-volatile memory transistor structure.
15. The voltage reference circuit of claim 12, further comprising:
a second NVM transistor coupled in a common source configuration with the first NVM transistor; and
a differential amplifier having inputs coupled to the first and second NVM transistors, and an output configured to provide the reference voltage.
16. The voltage reference circuit of claim 12, wherein the first NVM transistor is identical to the second NVM transistor and the semiconductor structure is a third NVM transistor identical to the first and second NVM transistors.
17. The voltage reference circuit of claim 12, wherein the semiconductor structure comprises an NVM transistor structure comprising:
a drain region, wherein the first switch is coupled between the drain region and the programming terminal;
a control gate coupled to the drain region;
a second floating gate coupled to the control gate.
18. The voltage reference circuit of claim 17, wherein the NVM transistor structure further comprises a source region commonly coupled to a source region of the first NVM transistor.
19. The voltage reference circuit of claim 12, further comprising a bias transistor configured to introduce a current through the semiconductor structure, which is equal to a current through the first NVM transistor.