1.-21. (canceled)
22. A layer system, comprising
a substrate;
a metallic bonding layer arranged on the substrate which consists of an NiCoCrAlX alloy;
an inner yttrium-stabilized zirconium oxide layer arranged on the metallic bonding layer; and
an outer ceramic layer arranged on the inner ceramic layer comprising at least 80 wt % of a pyrochlore phase, wherein the pyrochlore phase is Gd2Zr2O7 or Gd2Zr2O7.
23. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness between 10% and 50% of a total layer thickness of the inner layer plus the outer layer.
24. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 10% and 40% of the total layer thickness of the inner layer plus the outer layer.
25. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 10% and 30% of the total layer thickness of the inner layer plus the outer layer.
26. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 10% and 20% of the total layer thickness of the inner layer plus the outer layer.
27. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 20% and 50% of the total layer thickness of the inner layer plus the outer layer.
28. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 20% and 40% of the total layer thickness of the inner layer plus the outer layer.
29. The layer system claimed in claim 22, wherein the inner layer has a layer thickness of between 20% and 30% of the total layer thickness of the inner layer plus the outer layer.
30. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 30% and 50% of the total layer thickness of the inner layer plus the outer layer.
31. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 30% and 40% of the total layer thickness of the inner layer plus the outer layer.
32. The layer system as claimed in claim 22, wherein the inner layer has a layer thickness of between 40% and 50% of the total layer thickness of the inner layer plus the outer layer.
33. The layer system as claimed in claim 22, wherein the inner layer (10) has a layer thickness of 40 \u03bcm to 60 \u03bcm.
34. The layer system as claimed in claim 22, wherein the metallic bonding layer has the composition (in wt %):
11%-13% cobalt,
20%-22% chromium,
10.5%-11.5% aluminum,
0.3%-0.5% yttrium,
1.5%-2.5% rhenium, and
remainder nickel.
35. The layer system as claimed in claim 22, wherein the metallic bonding layer has the composition (in wt %):
24%-26% cobalt,
16%-18% chromium,
9.5%-10.5% aluminum,
0.3%-0.5% yttrium,
1.0%-2.0% rhenium, and
remainder nickel.
36. The layer system as claimed in claim 22, wherein the metallic bonding layer has the composition (in wt %):
29%-31% nickel,
27%-29% chromium,
7%-9% aluminum,
0.5%-0.8% yttrium,
0.6%-0.8% silicon, and
remainder cobalt.
37. The layer system as claimed in claim 22, wherein the metallic bonding layer has the composition (in wt %):
27%-29% nickel,
23%-25% chromium,
9%-11% aluminum,
0.3%-0.7% yttrium, and
remainder cobalt.
38. The layer system as claimed in claim 22, wherein the yttrium-stabilized zirconium oxide layer comprises 6 wt %-8 wt % of yttrium.
39. The layer system as claimed in claim 22, wherein the total layer thickness of the inner layer plus the outer layer is 300 \u03bcm.
40. The layer system as claimed in claim 22, wherein the total layer thickness of the inner layer plus the outer layer is 400 \u03bcm.
41. The layer system as claimed in claim 22, wherein the total layer thickness is at most 600 \u03bcm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a semiconductor device, comprising:
preparing a semiconductor substrate including a memory cell region having a memory cell transistor and a peripheral circuit region having a high voltage transistor;
forming a first insulating film above the semiconductor substrate situated in the memory cell region and a second insulating film thicker than the first insulating film above the semiconductor substrate situated in the peripheral circuit region;
forming a polysilicon film on the first and the second insulating films;
forming a silicon nitride film on the polysilicon film;
forming a mask pattern on the silicon nitride film for defining a plurality of openings for forming element isolation trenches in the memory cell region and the peripheral circuit region;
removing the polysilicon film according to the mask pattern to expose the first and the second insulating films;
completely removing the exposed first insulating film in the memory cell region to expose the semiconductor substrate and partially removing the exposed second insulating film in the peripheral circuit region such that a predetermined thickness of the exposed second insulating film remains unremoved;
etching the exposed semiconductor substrate in the memory cell region to form a trench having a first depth;
removing the remaining second insulating film in the peripheral circuit region to expose the semiconductor substrate;
simultaneously etching the exposed semiconductor substrate in the peripheral circuit region and the trench formed in the memory cell region to form a first element isolation trench having a second depth greater than the first depth in the memory cell region and a second element isolation trench having a third depth less than the second depth in the peripheral circuit region; and
filling an element isolation insulating film in the first and the second element isolation trenches.
2. The method according to claim 1, wherein the element isolation insulating film is a silicon oxide film comprising a hard polysilazane coated film.
3. The method according to claim 1, wherein the second insulating film is formed in a portion where the semiconductor substrate is lowered by a predetermined depth.
4. A method of manufacturing a semiconductor device comprising:
preparing a semiconductor substrate including a memory cell region having a memory cell transistor, a first peripheral circuit region having a low voltage transistor, a second peripheral circuit region having a high voltage transistor;
forming a first insulating film above the semiconductor substrate situated in the memory cell region and above the semiconductor substrate situated in a portion of the first peripheral circuit region where a gate electrode of the low voltage transistor is formed, and forming a second insulating film thicker than the first insulating film above a portion of the semiconductor substrate in the first peripheral circuit region where an element isolation trench is ultimately formed and above the semiconductor substrate situated in the second peripheral circuit region;
forming a first polysilicon film on the first and the second insulating films;
forming a silicon nitride film on the first polysilicon film;
forming a mask pattern on the silicon nitride film for defining a plurality of openings for forming element isolation trenches in the memory cell region, the first peripheral circuit region and the second peripheral circuit region;
removing the first polysilicon film according to the mask pattern to expose the first and the second insulating films;
completely removing the first insulating film in the memory cell region to expose the semiconductor substrate and partially removing the second insulating film in the first and the second peripheral circuit regions such that a predetermined thickness of the exposed second insulating film remains unremoved;
etching the exposed semiconductor substrate in the memory cell region to define a trench having a first depth;
removing the remaining second insulating film in the first and the second peripheral circuit regions to expose the semiconductor substrate;
simultaneously etching the exposed semiconductor substrate in the first and the second peripheral circuit regions and the trench formed in the memory cell region to form a first element isolation trench having a second depth greater than the first depth in the memory cell region and a second element isolation trench having a third depth less than the second depth in the first peripheral circuit region, and a third element isolation trench having a fourth depth less than the second depth in the second peripheral circuit region; and
filling an element isolation insulating film in the first, second, and the third element isolation trenches.
5. The method according to claim 4, wherein the element isolation insulating film is a silicon oxide film comprising a hard polysilazane coated film.
6. The method according to claim 4, wherein the second insulating film is formed in a portion where the semiconductor substrate is lowered by a predetermined depth.
7. The method according claim 4, wherein a depth of a bottom surface of the second element isolation trench measured from an interface between the first insulating film formed in the first peripheral circuit region and the semiconductor substrate is greater than a depth of a bottom surface of the third element isolation trench measured from an interface between the second insulating film formed in the second peripheral circuit region and the semiconductor substrate.
8. The method according to claim 4, wherein partially removing the exposed second insulating film in the first and the second peripheral circuit regions is carried out by etching with controlled etch time.
9. The method according to claim 5, wherein in the memory cell region, an upper portion of the silicon oxide film protrudes above an upper surface of the semiconductor substrate and an upper surface of the upper portion of the silicon oxide film is lower than an upper surface of the first polysilicon film.
10. The method according to claim 5, wherein in the first and the second peripheral circuit regions, an upper surface of the silicon oxide film is configured to be at level with an upper surface of the first polysilicon film.
11. The method according to claim 9, wherein in the memory cell region, an interelectrode insulating film is formed on the first polysilicon film and a second polysilicon film is formed on the interelectrode insulating film.
12. The method according to claim 10, wherein in the first and the second peripheral circuit regions, a second polysilicon film is formed on the first polysilicon insulating film.
13. The method according to claim 11, wherein the interelectrode insulating film comprises laminated layers of a first silicon oxide film, a silicon nitride film formed on the first silicon oxide film and a second silicon oxide film formed on the silicon nitride film; or an alumina film; or laminated layers of a first silicon nitride film, a first silicon oxide film formed on the first silicon nitride film, a second silicon nitride film formed on the first silicon oxide film, a second silicon oxide film formed on the second silicon nitride film, and a third silicon nitride film formed on the second silicon oxide film.
14. The method according to claim 4, wherein the semiconductor substrate comprises a silicon substrate, the first and the second insulating films comprise a silicon oxide film.
15. The method according to claim 14, wherein etching the exposed semiconductor substrate to the first depth is carried out by dry etching the silicon substrate with selectivity to silicon over silicon oxide film and by using the remaining second insulating film comprising the silicon oxide film as an etch stopper.
16. The method according to claim 14, wherein forming the silicon oxide film on the silicon substrate includes:
forming a sacrificial film on the silicon substrate;
forming a first mask on the sacrificial film in the memory cell region and on the sacrificial film over the first peripheral circuit region exclusive of a portion where an element isolation region is ultimately formed;
removing the sacrificial film in the first peripheral region according to the first mask, and the sacrificial film in the second peripheral region without the first mask to expose the semiconductor substrate,
etching the exposed silicon substrate to a predetermined depth;
removing the first mask formed in the memory cell region and the first peripheral circuit region;
forming a first silicon oxide film serving as a gate insulating film of the high voltage transistor by thermal oxidation on a portion of the silicon substrate situated in the first peripheral circuit region which has been etched and on the silicon substrate situated in the second peripheral circuit region;
removing the sacrificial film formed in the memory cell region and the first peripheral circuit region;
forming a second mask on the first silicon oxide film formed on the first peripheral circuit region and on the second peripheral circuit region;
forming a second silicon oxide film serving as a tunnel insulating film of the memory cell transistor and a gate insulating film of the low voltage transistor by thermal oxidation above the silicon substrate situated in the memory cell region and the first peripheral circuit region which are not covered by the second mask; and
removing the second mask in the first and the second peripheral circuit regions.
17. The method according to claim 4, wherein forming the mask pattern on the silicon nitride film to define openings to form the element isolation trenches is carried out by photolithography and dry etching the silicon nitride film.
18. The method according to claim 17, wherein the photolithography permits misalignment in which a width of the second insulating film in the first peripheral circuit region is narrower than a width of the element isolation trenches, and the second insulating film in the first peripheral circuit region is disposed within the element isolation trenches.
19. The method according to claim 4, wherein the semiconductor device is a NAND flash memory.
20. The method according to claim 19, wherein the NAND flash memory includes a metal oxide nitride oxide semiconductor gate structure.