1. A method of manufacturing a semiconductor device comprising a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, the method comprising:
forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region;
forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole;
forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and
forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole.
2. The method according to claim 1, further comprising:
forming an interconnection groove in the insulating layer, wherein a top face of the contact plug is exposed and the second contact hole is provided in a bottom face of the interconnection groove.
3. The method according to claim 2, wherein the interconnection groove is formed so that a portion of the contact plug protrudes from the bottom face thereof.
4. The method according to claim 2, wherein the interconnection is formed within the interconnection groove.
5. The method according to claim 1, wherein the contact plug is made of polycrystalline silicon and contains a higher concentration of p-type impurities than the p-type semiconductor region.
6. The method according to claim 1 wherein a silicide layer is formed between a top face of the contact plug and the interconnection, and between the n-type semiconductor region and the interconnection.
7. The method according to claim 1, further comprising:
ion-implanting carbon into a top face of the contact plug.
8. The method according to claim 7, wherein the implantation layer of carbon and a silicide layer are formed on a top face of the contact plug.
9. The method according to claim 1, further comprising:
ion-implanting carbon into a bottom of the first contact hole.
10. The method according to claim 1 wherein the contact plug further includes carbon.
11. The method according to claim 1, further comprising: forming a silicon nitride film having a thickness of not greater than 1 nm between the contact plug and the p-type semiconductor region.
12. The method according to claim 1, further comprising: forming a silicon nitride film on a surface of the insulating layer in the first contact hole.
13. The method according to claim 1, wherein the interconnection is a metal interconnection.
14. The method according to claim 1, wherein the interconnection includes a titanium (Ti) film contacting the contact plug and the n-type semiconductor region.
15. The method according to claim 1, wherein the interconnection includes a high melting point metal.
16. A semiconductor device comprising:
a memory array provided on a substrate;
a control circuit provided on the substrate between the substrate and the memory array;
an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit;
a contact plug provided within a first contact hole communicating from a surface of the insulating layer to the p-type semiconductor region, the contact plug being in contact with the p-type semiconductor region; and
an interconnection connected to the contact plug and to the n-type semiconductor region exposed within a second contact hole communicating from the surface of the insulating layer to the n-type semiconductor region.
17. The device according to claim 16, wherein a carbon implanted layer and a silicide layer are provided on a top face of the contact plug.
18. The device according to claim 16, wherein a carbon implanted layer is provided on a portion of the p-type semiconductor region in contact with the contact plug.
19. The device according to claim 16, wherein the contact plug faces the insulating layer via a silicon nitride film on the side face of the first contact hole.
20. The device according to claim 16, wherein a silicon nitride film is provided on a portion of the p-type semiconductor region in contact with the contact plug.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A trigger system for a paintball marker, comprising:
a micro-switch actuator;
a lever having a first end in contact with the micro-switch; and
a string connected to a second end of the lever and to a trigger guard.
2. The trigger system of claim 1, wherein the string is detachably connected to the lever.
3. The trigger system of claim 1, wherein the string is taut between the lever and the trigger guard.
4. The trigger system of claim 3, further including a bead is threaded though the string.
5. A trigger system for a paintball marker, comprising:
an actuator; and
a string connected to the actuator for moving the actuator.
6. The trigger system of claim 5, wherein the actuator includes a micro-switch.
7. The trigger system of claim 6, wherein the actuator includes a lever having a first end in contact with the micro-switch.
8. The trigger system of claim 7, wherein the lever has a second end attached to the string.
9. The trigger system of claim 8, wherein the string is held taut.
10. The trigger system of claim 9, wherein the string is detachable from the lever.
11. The trigger system of claim 10, wherein the string is attached to the trigger guard.
12. The trigger system of claim 11, further including a bead threaded onto the string.
13. A trigger system for a paintball marker, comprising:
a taut string; and
an actuator connected to one end of the string.
14. The trigger system of claim 13, further including a trigger guard attached to a second end of the string.
15. The trigger system of claim 14, wherein the string is detachable.
16. The trigger system of claim 15, wherein the actuator includes a switch.
17. The trigger system of claim 16, wherein the actuator includes a lever having a first end in contact with the switch and a second end attached to the string.