1. A manufacturing method of a MOS transistor, comprising:
providing a substrate; wherein a transistor is disposed in the substrate, the transistor comprises a gate dielectric layer, a gate on the gate dielectric layer and a sourcedrain region in the substrate at two sides of the gate;
forming a sacrificial layer on the substrate to cover the transistor;
removing a part of the sacrificial layer to expose the sourcedrain region; and
forming a silicide layer on the exposed sourcedrain region.
2. The manufacturing method of a MOS transistor as in claim 1, wherein when forming the silicide layer, the sacrificial layer levels with the gate.
3. The manufacturing method of a MOS transistor as in claim 1, wherein when forming the silicide layer, the sacrificial layer levels with the sourcedrain region.
4. The manufacturing method of a MOS transistor as in claim 1, wherein when forming the silicide layer, there is no sacrificial layer on the substrate.
5. The manufacturing method of a MOS transistor as in claim 1, further comprising forming at least a contact hole in the sacrificial layer to expose the sourcedrain region.
6. The manufacturing method of a MOS transistor as in claim 1, further comprising forming a dielectric layer on the sacrificial layer and forming at least a contact hole in the sacrificial layer and the dielectric layer to expose the sourcedrain region.
7. The manufacturing method of a MOS transistor as in claim 1, wherein the sacrificial layer comprises SOG, BARC, APF or photoresist.
8. The manufacturing method of a MOS transistor as in claim 1, wherein the step of forming the sourcedrain region comprises forming an epitaxial layer.
9. The manufacturing method of a MOS transistor as in claim 1, wherein the step of forming the silicide layer comprises:
performing a cleaning step;
forming a metal layer to at least cover the sourcedrain region;
performing an annealing process to make the metal layer react with the sourcedrain region; and
removing the metal layer not reacted with the sourcedrain region.
10. The manufacturing method of a MOS transistor as in claim 1, wherein the step of forming the transistor comprises:
forming a dummy gate on the substrate;
removing the dummy gate;
forming a high-k dielectric layer on the substrate;
performing an annealing process toward the high-k dielectric layer;
forming a low resistance layer on the high-k dielectric layer; and
forming a protective layer on the surface of the low resistance layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A charging device for charging a main capacitor by rectifying an output voltage, which is boosted by a self-excited DC-DC converter, with a diode,
wherein a control circuit of the self-excited DC-DC converter is configured to terminate an excitation period and to enter a charging period for charging the main capacitor by transmitting energy from a primary side to a secondary side of an oscillation transformer when a current value flowing in the primary side of the oscillation transformer reaches a first predetermined value, and to resume the excitation period in a delay time after detecting that a value of current flowing in the secondary side of the oscillation transformer is lower than a second predetermined value,
and the delay time is set to be longer than a sum of a time from a time point when the value of current flowing in the secondary side of the oscillation transformer is lower than the second predetermined value to a time point when the current reaches zero and a reverse recovery time of the diode.
2. An application-specific integrated circuit used as a control circuit of the charging device according to claim 1,
wherein an excitation period is terminated when a voltage of a first external connection terminal reaches a first predetermined value, and
the excitation period is resumed in a delay time after detecting that a voltage of a second external connection terminal is lower than a second predetermined value.
3. An application-specific integrated circuit according to claim 2,
further comprising a time delay circuit for changing the delay time depending on voltage of the second external connection terminal, wherein a voltage is inputted in said terminal depending on the boosted output voltage of the charging device.
4. An application-specific integrated circuit according to claim 2, further comprising a time delay circuit for changing the delay time to a range of 300 ns to 450 ns when a voltage of the second external connection terminal is 100 volts, or more where a fully charged voltage is 300 volts, in the main capacitor of the charging device.