1. An ion implantation method comprising:
(a) implanting ions into a region of a substrate to form an ion implanted region; and
(b) depositing a porous capping layer on the ion implanted region, the porous capping layer comprising dispersed gas pockets.
2. A method according to claim 1 wherein (b) comprises depositing a porous capping layer comprising dispersed gas pockets that are microscopic gas pockets.
3. A method according to claim 1 wherein (b) comprises depositing a porous capping layer having at least one of the following properties:
(i) a porosity of at least 20%; or
(ii) a pore volume of at least 20%.
4. A method according to claim 1 wherein (b) comprises depositing a porous capping layer comprising silicon and oxygen.
5. A method according to claim 1 wherein (b) comprises depositing a porous capping layer comprising silicon dioxide.
6. A method according to claim 5 comprising depositing the silicon dioxide by energizing a process gas comprising silane and oxygen.
7. A method according to claim 1 comprising during (a) or (b) maintaining the substrate at a temperature of between about 25\xb0 C. and about 400\xb0 C.
8. A method according to claim 1 further comprising annealing the substrate to volatilize at least a portion of the porous capping layer.
9. A method according to claim 1 comprising annealing the substrate to volatilize at least 90% of the porous capping layer while retaining at least 60% of the implanted ions in the ion implanted region.
10. A method according to claim 1 wherein (a) comprises implanting ions comprising arsenic, boron or phosphorous, in a dosage from 1\xd71014 atomscm3 to 1\xd71017 atomscm3.
11. A method according to claim 1 wherein (a) comprises implanting arsenic ions by energizing a process gas comprising an arsenic-containing gas.
12. An ion implantation method comprising:
(a) implanting ions into a region of a substrate to form an ion implanted region;
(b) depositing a porous capping layer on the ion implanted region, the porous capping layer comprising dispersed microscopic gas pockets; and
(c) annealing the substrate to volatilize at least 80% of the porous capping layer overlying the ion implanted region during the annealing process.
13. A method according to claim 12 wherein (b) comprises depositing a porous capping layer having at least one of the following properties:
(i) a porosity of at least 20%; or
(ii) a pore volume of at least 20%.
14. A method according to claim 12 wherein (b) comprises depositing a porous capping layer comprising silicon and oxygen.
15. A method according to claim 12 wherein (b) comprises depositing a porous capping layer comprising silicon dioxide.
16. An ion implantation method comprising:
(a) implanting arsenic ions into a region of a substrate to form an ion implanted region;
(b) depositing on the ion implanted region, a porous capping layer comprising silicon-containing material having dispersed microscopic gas pockets; and
(c) annealing the substrate to volatilize at least 80% of the porous capping layer overlying the ion implanted region during the annealing process.
17. A method according to claim 16 wherein (b) comprises depositing a porous capping layer comprising silicon dioxide.
18. A method according to claim 16 wherein (a) comprises implanting the arsenic ions using a process gas comprising arsenic fluoride or arsenic hydride.
19. A method according to claim 16 wherein (a) comprises maintaining the substrate at a temperature of between about 25\xb0 C. and about 400\xb0 C.
20. A method according to claim 16 wherein (c) comprises annealing the substrate to a temperature of from about 800\xb0 C. to about 1300\xb0 C.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of making a memory cell, comprising:
forming a body on a substrate, said body extending vertically from said substrate;
forming a first gate comprising a vertical member and a horizontal member, wherein said first gate is disposed laterally from said body; and
forming a second gate comprising a vertical member and a horizontal member, wherein said second gate is disposed laterally from said first gate;
wherein said horizontal member of said first gate overlaps said horizontal member of said second gate.
2. The method of claim 1, further comprising forming a spacer layer having a width around said first gate, wherein said width determines a horizontal extension of said horizontal member of said first gate.
3. The method of claim 1, further comprising forming a first dielectric layer between said first gate and said body.
4. The method of claim 3, wherein forming said first dielectric comprises forming a vertical portion having a first thickness adjacent to said body and forming a horizontal portion having a second thickness adjacent to said substrate, wherein said second thickness is greater than said first thickness.
5. The method of claim 4, wherein forming said first dielectric comprises forming said first dielectric using a dopant enhanced oxidation process.
6. The method of claim 4, wherein forming said first dielectric comprises forming said first dielectric using a directional dielectric deposition process.
7. The method of claim 1, further comprising forming a second dielectric between said first and second gates.
8. The method of claim 7, wherein forming said second dielectric comprises forming an oxide-nitride-oxide.
9. The method of claim 1, further comprising forming a horizontal overlapping region of said first and second gates wherein a capacitive coupling ratio between said first and second gates is between 0.3 and 0.6.