1. A method of fabricating a semiconductor nanowire comprising:
forming at least one semiconductor nanowire from at least an uppermost semiconductor layer of a substrate, wherein an end segment of said at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of said at least one semiconductor nanowire is attached to a second semiconductor pad region;
performing a first hydrogen anneal on said at least one semiconductor nanowire with at least a bottommost surface of said at least one semiconductor nanowire in direct contact with an uppermost surface of said substrate;
removing a portion of said substrate located beneath said at least one semiconductor nanowire to suspend said at least one semiconductor nanowire above a remaining portion of said substrate; and
performing a second hydrogen anneal on said at least one semiconductor nanowire that is suspended above the remaining portion of said insulator layer.
2. The method of claim 1, wherein during said first hydrogen anneal, an uppermost surface of the at least one semiconductor material is protected by a patterned mask.
3. The method of claim 1, wherein said first hydrogen anneal is performed at a temperature from 600\xb0 C. to 1000\xb0 C. at a hydrogen pressure of from 7 torr to 600 torr.
4. The method of claim 1, wherein said removing the portion of said substrate located beneath said at least one semiconductor nanowire comprises an isotropic etching process.
5. The method of claim 1, wherein said second hydrogen anneal is performed at a temperature from 600\xb0 C. to 1000\xb0 C. at a hydrogen pressure of from 7 torr to 600 torr.
6. The method of claim 1, wherein said first hydrogen anneal is performed at a temperature, pressure or temperature and pressure which is greater than a temperature, pressure or temperature and pressure of said second hydrogen anneal.
7. The method of claim 1, further comprising performing an oxidation process at a temperature of greater than 700\xb0 C. and etching grown oxide to thin said at least one semiconductor nanowire after performing said second hydrogen anneal.
8. The method of claim 1, further comprising growing a chemical oxide from the at least one semiconductor nanowire and etching grown oxide to thin said at least one semiconductor nanowire after performing said second hydrogen anneal.
9. The method of claim 1, wherein said at least one semiconductor nanowire prior to performing said first hydrogen anneal has a first roughness, said at least one semiconductor nanowire after said performing the first hydrogen anneal and prior to performing the second hydrogen anneal has a second roughness, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third roughness, wherein said first roughness is greater than the second roughness, and said second roughness is greater than the third roughness.
10. The method of claim 9, wherein said first roughness, expressed in terms of a mean squared roughness, is from 0.5 nm to 5 nm, said second roughness, expressed in terms of a mean squared roughness, is from 0.3 nm to 2 nm, and said third roughness, expressed in terms of a mean squared roughness, is from 0.1 nm to 1 nm.
11. The method of claim 1, wherein said at least one semiconductor nanowire prior to performing said first hydrogen anneal has a first width, said at least one semiconductor nanowire after performing said first hydrogen anneal and prior to performing said second hydrogen anneal has a second width, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third width, wherein said first width, said second width and said third width are substantially the same.
12. The method of claim 1, wherein said at least one semiconductor nanowire after performing said first hydrogen anneal and prior to performing said second hydrogen anneal has a second width, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third width, wherein said second width is greater than said third width.
13. The method of claim 1, wherein said at least one semiconductor nanowire after performing said first hydrogen anneal and prior to performing said second hydrogen anneal has a second width, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third width, wherein said second width is less than said third width.
14. The method of claim 1, wherein said at least one semiconductor nanowire comprises a plurality of semiconductor nanowires, wherein a pitch between each of the semiconductor nanowires is from 5 nm to 70 nm.
15. The method of claim 1, wherein substrate further includes at least one other semiconductor layer beneath the uppermost semiconductor layer, said at least one other semiconductor layer comprises a different semiconductor material than the uppermost semiconductor layer.
16. The method of claim 1, wherein said substrate further includes an insulator layer located directly beneath the uppermost semiconductor layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A readback system, comprising:
a magnetic sensor that receives a sensor current, the sensor sensing magnetic bits at a bit frequency, and generating a sensor output; and
a channel circuit that modulates the sensor current at a modulation frequency higher than the bit frequency, the circuit sampling the sensor output and combining multiple samples of the sensor output per magnetic bit into a combined sample output.
2. The readback system of claim 1 where in the magnetic sensor comprises a magnetoresistive sensor sensing magnetic bits stored on perpendicular magnetic recording media.
3. The readback system of claim 2 wherein a magnitude of the sensor current and a magnitude of a magnetic field from the magnetic bits are sufficiently small that the sensor output comprises amplitudes that do not exceed a multiplying range of the sensor output.
4. The readback system of claim 1 wherein the sensor output comprises an amplitude that is representative of a product of the magnitude of the modulated sensor current and a magnitude of a magnetic field from the magnetic bits.
5. The readback system of claim 1, wherein the channel circuit comprises:
a timing circuit generating a modulation timing output that modulates the sensor current at a timing frequency that is a multiple of the bit frequency, the timing circuit generating a sampling output that defines multiple sample times per magnetic bit; and
a sampler circuit that receives the sensor output and the sampling output and that generates the combined sample sampler output in which the multiple samples per magnetic bit are combined into a single sample per magnetic bit.
6. The readback system of claim 5, wherein the timing circuit receives an amplified sample of the sensor output, and the timing circuit synchronizes the timing of the modulation timing output during a synchronization interval as a function of the amplified sample.
7. The readback system of claim 6 wherein the modulation of the sensor current is turned off during the synchronization interval, and turned on after the synchronization interval.
8. The readback system of claim 1 wherein the channel circuit further comprises:
a local oscillator oscillating at the modulation frequency and an LC circuit that resonates at the modulation frequency, the local oscillator and the LC circuit coupling to the magnetic sensor to provide the modulation of the sensor current; and
a demodulator circuit coupled to the sensor output and generating the combined sample output.
9. The readback system of claim 1 wherein the modulation of the sensor current comprises sinusoidal modulation.
10. The readback system of claim 1 wherein the modulation of the sensor current comprises pulse modulation.
11. A readback system, comprising:
a magnetoresistive sensor that receives a first portion of a sensor current at a magnetoresistive element in the magnetoresistive sensor, and that receives a second portion of a sensor current at a winding in the magnetoresistive sensor the sensor sensing magnetic bits at a bit frequency, and generating a sensor output; and
a channel circuit that modulates at least one of the portions of the sensor current at a modulation frequency higher than the bit frequency, the circuit sampling the sensor output and combining multiple samples of the sensor output per magnetic bit into a combined sample output.
12. The readback system of claim 11, wherein the winding receives a DC portion of the sensor current.
13. The readback system of claim 11, wherein the magnetoresistive element receives a modulated portion of the sensor current.
14. the readback system of claim 11 wherein the magnetoresistive sensor receives a DC portion of the sensor current.
15. The readback system of claim 11 wherein the channel circuit comprises a synchronous demodulator circuit.
16. The readback system of claim 11 wherein the channel comprises a resonant LC circuit with a Q factor, and the magnetoresistive element is coupled to the resonant LC circuit and has a modulated resistance that modulates the Q factor.
17. A readback system, comprising:
a magnetoresistive sensor modulating a sensor output as a linear product of a sensor current applied to the magnetoresistive sensor and a magnetic field applied to the sensor by saturated magnetic bits moving relative to the sensor at a bit frequency; and
a channel circuit that modulates the sensor current at a modulation frequency that is higher than the bit frequency; the channel circuit receiving the sensor output and demodulating the sensor output to provide multiple samples per magnetic bit, and the channel circuit combining the multiple samples per bit into a combined sample output.
18. The readback system of claim 17 wherein the magnetoresistive sensor comprises a tunneling magnetoresistive sensor.
19. the readback system of claim 17 wherein the magnetoresistive sensor comprise a giant magnetoresistive sensor.
20. the readback system of claim 17 wherein the channel circuit demodulates the sensor output with a synchronous demodulator circuit.