1. A microprocessor comprising:
one or more front-end circuits and one or more execution circuits, at least one of the execution circuits being operable in at least a single-thread mode and a multiple-thread mode and capable of simultaneously retaining architectural state of at least two threads of a plurality of threads;
an interconnection circuit enabled to provide selective communication between each of the front-end circuits and each of the execution circuits;
a memory circuit enabled to provide access to external memory by each of the front-end circuits and one or more of the execution circuits;
a master control circuit;
wherein with respect to the interconnection circuit, the front-end circuits, and the execution circuits, the master control circuit is enabled during microprocessor initialization to establish selected unestablished characteristics of a first set of microarchitecture characteristics and further enabled to subsequently alter selected characteristics of a second set of microarchitecture characteristics based at least in part on a plurality of samples over time of at least one type of behavior measurement;
wherein for each of a plurality of active threads to be processed of the plurality of threads, the master control circuit is enabled to establish a respective transient circuit collection allocated from unallocated portions of the circuits;
wherein each of the transient circuit collections is collectively enabled to fetch, decode, and execute its respective active thread; and
wherein at least one of the front-end circuits is operable to translate variable-length macro instructions to a plurality of operations, wherein at least some of the operations refer to at least some of the architectural state, the selective communication comprises parallel communication of at least a portion of the operations from the at least one front-end circuit simultaneously to a plurality of the execution circuits, and the plurality of execution units are operable to perform the portion of the operations at least in part in response to the communication thereof.
2. The microprocessor of claim 1, further comprising a non-volatile memory programmed with information based on tests performed during manufacture of the microprocessor and referenced by the master control circuit during the establishment of the selected characteristics of the first set of microarchitecture characteristics.
3. The microprocessor of claim 1, wherein the microprocessor is operable with a configuration store comprising at least one of a Read Only Memory (ROM) and a Randomly Accessible readwrite Memory (RAM).
4. The microprocessor of claim 3, wherein execution of a function by the microprocessor as specified by the configuration store directs the master control circuit to control the interconnection circuit and to configure the circuits.
5. The microprocessor of claim 1, wherein the execution circuits comprise an integer execution and control circuit.
6. The microprocessor of claim 5, wherein the integer execution and control circuit is enabled to direct pipeline processing of one or more of the operations.
7. The microprocessor of claim 1, wherein the execution circuits comprise at least one of a floating-point execution circuit, a segmentation circuit, and a reconfigurable circuit.
8. The microprocessor of claim 1, wherein the at least one type of behavior measurement comprises at least one of:
an available battery life measurement,
an available battery energy measurement,
a cache performance measurement,
an available spare processing cycles measurement,
a superscalar instruction issue measurement,
a speculative processing measurement,
an out-of-order processing measurement,
a power consumption measurement,
a temperature measurement,
a performance measurement, and
a power-performance measurement.
9. The microprocessor of claim 1, wherein the microprocessor is enabled to implement a general purpose computing system capable of high-performance while supporting a large base of software covering a wide variety of applications and while further supporting a wide variety of peripheral interfaces and devices.
10. A method comprising:
allocating as-yet unallocated computing resources to first and second transient circuit collections, each of the transient circuit collections having respective power-performance behavior;
based at least in part on a plurality of samples over time of at least one type of behavior measurement, dynamically reassigning an active thread from the first transient circuit collection for execution on the second transient circuit collection;
configuring a first one of the computing resources to operate in a single-thread mode;
configuring a second one of the computing resources to operate in a multiple-thread mode and to simultaneously retain architectural state of at least two threads;
translating variable-length macro instructions into operations executable by the computing resources and corresponding to the active thread, at least some of the operations referring to at least some of the architectural state;
communicating in parallel at least a portion of the operations to a plurality of the computing resources simultaneously, and in response to the portion of the operations, the plurality of computing resources performing the portion of the operations;
wherein at least one of the acts of configuring is according to at least one of a static technique and a dynamic technique;
wherein the first computing resource is allocated to the first transient circuit collection; and
wherein the second computing resource is simultaneously allocated to the first and the second transient circuit collections.
11. The method of claim 10, wherein the dynamically reassigning is directed to improve at least one of
performance of the active thread,
power consumed during processing of the active thread,
power-performance of the active thread, and
a maximum temperature of one of the computing resources.
12. The method of claim 10, wherein the dynamically reassigning is based at least in part on an event.
13. The method of claim 12, wherein the event comprises at least one of
a thread activation,
a thread deactivation,
a high-temperature detection,
a low-temperature detection,
a low-power detection,
a switching to battery power,
a switching from battery power,
a low battery life detection,
a low battery energy detection,
a switching to wall power,
a switching from wall power,
a request for high-performance operation, and
a request for long-duration operation.
14. The method of claim 10, further comprising assessing a metric.
15. The method of claim 14, wherein the metric comprises at least one of
an available battery life metric,
an available battery energy metric,
a cache performance metric,
an available spare processing cycles metric,
a superscalar instruction issue metric,
a speculative processing metric,
an out-of-order processing metric,
a power consumption metric,
a temperature metric,
a performance metric, and
a power-performance metric.
16. The method of claim 14, wherein the dynamically reassigning is based at least in part on a function of the metric.
17. The microprocessor of claim 10, wherein the at least one type of behavior measurement comprises at least one of:
an available battery life measurement,
an available battery energy measurement,
a cache performance measurement,
an available spare processing cycles measurement,
a superscalar instruction issue measurement,
a speculative processing measurement,
an out-of-order processing measurement,
a power consumption measurement,
a temperature measurement,
a performance measurement, and
a power-performance measurement.
18. A computer-readable medium having a set of instructions stored therein which when executed by a processing element causes the processing element to perform functions comprising:
based at least in part on a plurality of samples over time of at least one type of behavior measurement, arranging to execute a first thread on a first set of execution units from a pool of execution units;
arranging to execute a second thread on a second set of execution units from the pool of execution units;
wherein each of the threads corresponds to respective sequences of operations produced by translating respective first and second sequences of variable-length macro instructions;
wherein at least a multiple-thread capable one of the first set of execution units is included in the second set of execution units and is capable of performing in parallel at least one respective operation from each of the sequences of operations, and is further capable of simultaneously retaining architectural state of at least the first and the second threads, at least some of the operations referring to at least some of the architectural state;
wherein the arranging to execute the first thread comprises configuring a routing network to deliver the operations of the first thread to the first set of execution units, and the arranging to execute the second thread comprises configuring the routing network to deliver the operations of the second thread to the second set of execution units, and to simultaneously deliver at least a portion of the operations of the second thread in parallel to the second set of execution units; and
wherein in response to the delivery of particular ones of the operations, the execution units are adapted to perform the particular operations.
19. The computer-readable medium of claim 18, wherein the first set of execution units comprises at least one of
an integer execution unit,
a floating-point execution unit,
a segmentation unit,
a special-purpose unit,
a memory interface unit, and
a reconfigurable unit.
20. The computer-readable medium of claim 18, further comprising arranging to execute a third thread on the first set of execution units.
21. The computer-readable medium of claim 2, further comprising saving context associated with the first thread from the first set of execution units.
22. The computer-readable medium of claim 21, wherein the saving context saves all context associated with the first thread.
23. The computer-readable medium of claim 21, wherein the saving context omits at least some context associated with the first thread.
24. The microprocessor of claim 18, wherein the at least one type of behavior measurement comprises at least one of:
an available battery life measurement,
an available battery energy measurement,
a cache performance measurement,
an available spare processing cycles measurement,
a superscalar instruction issue measurement,
a speculative processing measurement,
an out-of-order processing measurement,
a power consumption measurement,
a temperature measurement,
a performance measurement, and
a power-performance measurement.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A polymer composition for the manufacture of pipes having a design stress of at least 9.0 MPa (PE112) comprising 92-99% wt of a bimodal ethylene polymer and 1-8% wt of carbon black, said composition being characterised by having MFR5 in the range 0.15 to 0.40 g10 min and a density in the range 955 to 965 kgm3, said polymer being composed of 42-55% wt of a low molecular weight ethylene homopolymer having MFR2 in the range 350 to 1500 g10 min and 58-45% wt of a high molecular weight copolymer of ethylene with 1-hexene, 4-methyl-1-pentene, 1-octene andor 1-decene.
2. A composition according to claim 1 wherein the said polymer is composed of 42-52% wt of said homopolymer and 58-48% wt of said copolymer.
3. A composition according to claim 1 or claim 2 wherein the said polymer is composed of 45-50% wt of said homopolymer and 55-50% wt of said copolymer.
4. A composition according to any preceding claim wherein said MFR5 range is 0.15 to 0.30 g10 min.
5. A composition according to any preceding claim wherein said carbon black comprises 20-60% wt of a master batch which further comprises a carrier therefor.
6. A composition according to any preceding claim wherein said homopolymer consists to the extent of at least 97% wt of ethylene monomer units.
7. A composition according to any preceding claim wherein said copolymer has a molecular weight of at least 3500.
8. A composition according to any preceding claim which has a Charpy impact strength at 0 C. of at least 10 kJm2.
9. A composition according to any preceding claim which comprises 97.0 to 98.5% wt of said polymer and 1.5 to 3% wt of carbon black.
10. A composition according to any preceding claim which has a density of between 958 and 963 kgm3.
11. A composition according to any preceding claim wherein said bimodal polymer has an MFR5 of 0.1 to 1.0 g10 min.
12. A composition according to any preceding claim wherein said bimodal polymer has a density of at least 953 kgm3.
13. A composition according to any preceding claim wherein said composition has an FFR215 of at least 38.
14. A method of producing pipes which comprises extruding a composition according to any of claims 1 to 13 over a mandrel and a die and thereafter enlarging the diameter of the extruded pipe to a predetermined value.
15. A method according to claim 14 wherein the enlargement is effected by means of a floating plug mandrel.
16. A method according to claim 14 wherein the enlargement is effected by pulling the pipe through a heated vacuum sizing chamber.
17. Pipes formed of the composition claimed in any of claims 1 to 13 and having a design stress of at least 9.0 MPa.
18. Pipes according to claim 17 having a design stress of at least 10.0 MPa.
19. Pipes according to claim 17 or claim 18 having slow crack propagation resistance of at least 1000 hours at 4.6 MPa loop stress at 80 C.
20. Pipes according to any of claims 17 to 19 having slow crack propagation resistance of at least 800 hours at 4.9 MPa loop stress at 80 C.
21. Pipes according to any of claims 17 to 20 which have a critical temperature of no higher than 7 C.
22. Pipes according to any of claims 17 to 21 which have a critical temperature of no higher than 10 C.
23. Pipes according to any of claims 17 to 22 which have a modulus of elasticity of at least 800 MPa.