1. A method for forming a write once read only memory cell, comprising:
forming a metal oxide semiconductor field effect transistor (MOSFET); wherein forming the MOSFET includes:
forming a first sourcedrain region, a second sourcedrain region, and a channel region between the first and the second sourcedrain regions in a substrate;
forming a gate insulator above the channel region; and
forming a gate above the gate insulator;
forming an array plate;
forming a conductive plug coupling the first sourcedrain region to the array plate;
forming a bitline coupled to the second sourcedrain region such that the write once read only memory cell can be programmed in a reverse direction to have a trapped charge in the gate insulator adjacent to the first sourcedrain region by biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the gate by a wordline address, and wherein the programmed MOSFET will operate at reduced drain source current in a forward direction.
2. The method of claim 1, wherein forming a gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
3. The method of claim 2, wherein forming a gate insulator above the channel region includes forming a gate insulator selected from the group of silicon dioxide formed by wet oxidation, silicon oxynitride, silicon rich oxide, and aluminum oxide.
4. The method of claim 1, wherein forming a gate insulator above the channel region includes forming a composite gate layer.
5. The method of claim 4, wherein forming a composite gate layer includes forming a composite gate layer having a silicon dioxide layer and a silicon nitride layer.
6. The method of claim 4, wherein forming a composite gate layer includes forming a composite gate layer having a silicon dioxide and an aluminum oxide layer.
7. The method of claim 1, wherein forming a gate insulator above the channel region includes forming a multiple layer of oxide-nitride-oxide.
8. The method of claim 1, wherein forming a gate insulator above the channel region includes forming the gate insulator with implanted oxides having traps.
9. A method for forming a memory device, comprising:
forming a transistor, including:
forming a first sourcedrain region, a second sourcedrain region, and a channel region between the first and the second sourcedrain regions in a substrate;
forming a gate insulator above the channel region;
forming a gate above the gate insulator;
forming an array plate;
forming a conductive plug coupling the first sourcedrain region to the array plate;
forming a bitline coupled to the second sourcedrain region; and
configuring a circuit in the memory device to program the memory cell in a reverse direction with a trapped charge in the gate insulator adjacent to the first sourcedrain region.
10. The method of claim 9, wherein, configuring the circuit in the memory device includes biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the gate by a wordline address, and wherein the transistor will operate at reduced drain source current in a forward direction.
11. The method of claim 9, wherein forming a gate insulator above the channel region includes forming a gate insulator selected from the group of silicon oxide, silicon oxynitride, silicon rich oxide, and aluminum oxide.
12. The method of claim 9, wherein forming a gate insulator above the channel region includes forming a composite gate insulator including:
a layer of silicon dioxide; and
a layer of silicon nitride.
13. The method of claim 9, wherein forming a gate insulator above the channel region includes forming a composite gate insulator including:
a layer of silicon dioxide; and
a layer of aluminum oxide.
14. The method of claim 9, wherein forming a gate insulator above the channel region includes forming an oxide-nitride-oxide layer structure.
15. The method of claim 9, wherein forming a gate insulator above the channel region includes implanting an impurity element into a gate insulator material.
16. A method for forming a memory device, comprising:
forming a transistor, including:
forming a first sourcedrain region, a second sourcedrain region, and a channel region between the first and the second sourcedrain regions in a substrate;
forming a composite gate insulator above the channel region including a layer of silicon dioxide and a layer of silicon nitride;
forming a gate above the composite gate insulator;
forming an array plate;
forming a conductive plug coupling the first sourcedrain region to the array plate;
forming a bitline coupled to the second sourcedrain region; and
configuring a circuit in the memory device to program the memory cell in a reverse direction with a trapped charge in the gate insulator adjacent to the first sourcedrain region.
17. The method of claim 16, wherein forming a composite gate insulator includes forming to a thickness of at least 10 nanometers (nm).
18. The method of claim 16, wherein, configuring the circuit in the memory device includes biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the gate by a wordline address, and wherein the transistor will operate at reduced drain source current in a forward direction.
19. A method for forming a memory device, comprising:
forming a transistor, including:
forming a first sourcedrain region, a second sourcedrain region, and a channel region between the first and the second sourcedrain regions in a substrate;
forming a composite gate insulator above the channel region including a layer of silicon dioxide and a layer of aluminum oxide;
forming a gate above the composite gate insulator;
forming an array plate;
forming a conductive plug coupling the first sourcedrain region to the array plate;
forming a bitline coupled to the second sourcedrain region; and
configuring a circuit in the memory device to program the memory cell in a reverse direction with a trapped charge in the gate insulator adjacent to the first sourcedrain region.
20. The method of claim 19, wherein forming a composite gate insulator includes forming to a thickness of at least 10 nanometers (nm).
21. The method of claim 19, wherein, configuring the circuit in the memory device includes biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the gate by a wordline address, and wherein the transistor will operate at reduced drain source current in a forward direction.
22. A method for forming a memory device, comprising:
forming a transistor, including:
forming a first sourcedrain region, a second sourcedrain region, and a channel region between the first and the second sourcedrain regions in a substrate;
forming a composite gate insulator above the channel region including an oxide-nitride-oxide layer structure;
forming a gate above the composite gate insulator;
forming an array plate;
forming a conductive plug coupling the first sourcedrain region to the array plate;
forming a bitline coupled to the second sourcedrain region; and
configuring a circuit in the memory device to program the memory cell in a reverse direction with a trapped charge in the gate insulator adjacent to the first sourcedrain region.
23. The method of claim 22, wherein forming a composite gate insulator includes forming to a thickness of at least 10 nanometers (nm).
24. The method of claim 22, wherein, configuring the circuit in the memory device includes biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the gate by a wordline address, and wherein the transistor will operate at reduced drain source current in a forward direction.
25. A method for forming a memory device, comprising:
forming a transistor, including:
forming a first sourcedrain region, a second sourcedrain region, and a channel region between the first and the second sourcedrain regions in a substrate;
implanting an impurity element into an insulator material to form a gate insulator above the channel region;
forming a gate above the gate insulator;
forming an array plate;
forming a conductive plug coupling the first sourcedrain region to the array plate;
forming a bitline coupled to the second sourcedrain region; and configuring a circuit in the memory device to program the memory cell in a reverse direction with a trapped charge in the gate insulator adjacent to the first sourcedrain region.
26. The method of claim 25, wherein forming a composite gate insulator includes forming to a thickness of at least 10 nanometers (nm).
27. The method of claim 25, wherein, configuring the circuit in the memory device includes biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the gate by a wordline address, and wherein the transistor will operate at reduced drain source current in a forward direction.
28. A method for forming an electronic system, comprising:
forming a processor;
forming a memory device, including:
forming a transistor in a memory cell; including
forming a first sourcedrain region, a second sourcedrain region, and a channel region between the first and the second sourcedrain regions in a substrate;
forming a gate insulator above the channel region;
forming a gate above the gate insulator;
forming an array plate;
forming a conductive plug coupling the first sourcedrain region to the array plate;
forming a bitline coupled to the second sourcedrain region; and
configuring a circuit in the memory device to program the memory cell in a reverse direction with a trapped charge in the gate insulator adjacent to the first sourcedrain region; and
coupling the processor to the memory device.
29. The method of claim 28, wherein forming the memory device includes forming a write once read only memory device.
30. The method of claim 28, wherein forming the gate insulator above the channel region includes forming a composite gate insulator above the channel region.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A molecular sensing device, comprising:
a substrate;
a well i) formed in a material that is positioned on a surface of the substrate or ii) formed in a surface of the substrate;
a signal amplifying structure positioned in the well; and
an immersion fluid deposited into the well and surrounding the signal amplifying structure.
2. The molecular sensing device as defined in claim 1 wherein the immersion fluid includes an inert gas, a liquid, or a liquid and a functional species dissolved in the liquid.
3. The molecular sensing device as defined in claim 1, further comprising a removable cover that seals the immersion fluid in the well when the removable cover is in a closed position.
4. The molecular sensing device as defined in claim 1 wherein the device includes:
an array of discrete wells i) formed in the material that is positioned on the surface of the substrate or ii) formed in the surface of the substrate;
a respective signal amplifying structure in each of the discrete wells.
5. The molecular sensing device as defined in claim 4 wherein:
the immersion fluid is the same in each of the discrete wells; or
the immersion fluid is different in each of the discrete wells; or
some of the discrete wells have the immersion fluid and some other of the discrete wells have one or more other immersion fluids that are different from the immersion fluid.
6. The molecular sensing device as defined in claim 4, further comprising a barrier wall fluidly separating at least two of the discrete wells in the array.
7. The molecular sensing device as defined in claim 4 wherein at least two of the respective signal amplifying structures are functionalized to be receptive to a different species.
8. The molecular sensing device as defined in claim 4 wherein the respective signal amplifying structures are the same in each of the discrete wells.
9. The molecular sensing device as defined in claim 1 wherein the signal amplifying structure is a Raman spectroscopy enhancing structure.
10. A method for using the molecular sensing device as defined in claim 1, the method comprising sealing the immersion fluid in the well by attaching a removable cover to the material on the surface of the substrate or to the substrate surface.
11. A surface enhanced Raman spectroscopy (SERS) system, comprising:
the molecular sensing device as defined in claim 1;
a solution containing a species to be introduced into the well of the molecular sensing device;
a laser source to emit light within a wavelength or a spectrum of wavelengths toward the well of the molecular sensing device; a photodetector to detect light that is scattered after the light from the laser source interacts with the species in the well, and to output a signal in response to detecting the scattered light;
a light filtering element positioned between the molecular sensing device and the photodetector; and
a light dispersion element positioned between the molecular sensing device and the photodetector.
12. A method for making a molecular sensing device, the method comprising:
forming a well i) in a material that is positioned on a surface of a substrate or ii) in the surface of the substrate;
forming a signal amplifying structure in the well; and
introducing an immersion fluid into the well such that the signal amplifying structure is surrounded by the immersion fluid.
13. The method as defined in claim 12 wherein the forming of the well and the forming of the signal amplifying structure occur simultaneously, and wherein the forming steps are accomplished by:
pressing a mold into a resist material that is positioned on the substrate, the mold having a pattern to form the well and the signal amplifying structure within the well;
while the mold is pressed into the resist material, at least partially curing the resist material;
removing the mold; and
depositing a signal-enhancing material on at least a surface of a base of the signal amplifying structure.
14. The method as defined in claim 12 wherein prior to introducing the immersion fluid, the method further comprises selecting the immersion fluid to include a predetermined functional ligand that is selective to a predetermined species.
15. The method as defined in claim 12, further comprising sealing the immersion fluid in the well by adhering a removable cover to the material on the surface of the substrate or to the substrate surface.