1. A computer implemented method of optimizing sequential data fetches in a computer system, the method comprising:
fetching a data segment from a main memory, the data segment having a plurality of target data entries;
extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and
storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number of target data entries in the data segment.
2. The method of claim 1, further comprising referencing the intermediate cache line buffer rather than the main memory upon a target data entry fetch miss condition at the target data cache.
3. The method of claim 1, further comprising maintaining an address compare register containing an address of the data segment in the intermediate cache line buffer.
4. The method of claim 3, wherein the address compare register includes a bit selectively set to indicate whether the data segment stored in the intermediate cache line buffer is valid.
5. The method of claim 4, further comprising referencing the intermediate cache line buffer for a second target data entry upon a target data entry fetch miss condition and comparing an address of the second target data entry to the address in the address compare register.
6. The method of claim 5, further comprising extracting a second portion of the data segment from the intermediate cache line buffer and storing the second portion of the data segment in the target data cache upon the comparison resulting in matched addresses, the second portion of the data segment having the second target data entry.
7. The method of claim 6, further comprising fetching a new data segment from the main memory upon an intermediate cache line buffer miss condition and storing the new data segment in the intermediate cache line buffer, the intermediate cache line buffer miss condition corresponding to the comparison resulting in unmatched addresses.
8. The method of claim 1, wherein the intermediate cache line buffer is an intermediate cache between the main memory and the target data cache, and wherein the plurality of target data entries comprises storage protection keys each associated with a chunk of data.
9. A system for optimizing sequential data fetches in a computer system, the system comprising:
a computer memory; and
one or more processors in communication with the computer memory, the one or more processors configured to perform a method comprising:
fetching a data segment from a main memory, the data segment having a plurality of target data entries;
extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and
storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number of target data entries in the data segment.
10. The system of claim 9, wherein the method further comprises referencing the intermediate cache line buffer rather than the main memory upon a target data entry fetch miss condition at the target data cache.
11. The system of claim 9, wherein the method further comprises maintaining an address compare register containing an address of the data segment in the intermediate cache line buffer.
12. The system of claim 11, wherein the address compare register includes a bit selectively set to indicate whether the data segment stored in the intermediate cache line buffer is valid.
13. The system of claim 12 wherein the method further comprises referencing the intermediate cache line buffer for a second target data entry upon a target data entry fetch miss condition and comparing an address of the second target data entry to the address in the address compare register.
14. The system of claim 13, wherein the method further comprises extracting a second portion of the data segment from the intermediate cache line buffer and storing the second portion of the data segment in the target data cache upon the comparison resulting in matched addresses, the second portion of the data segment having the second target data entry.
15. The system of claim 14, further comprising fetching a new data segment from the main memory upon an intermediate cache line buffer miss condition and storing the new data segment in the intermediate cache line buffer, the intermediate cache line buffer miss condition corresponding to the comparison resulting in unmatched addresses.
16. The system of claim 9, wherein the plurality of target data entries comprises storage protection keys each associated with a chunk of data.
17. A computer program product for optimizing sequential data fetches in a computer system, comprising:
a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
fetching a data segment from a main memory, the data segment having a plurality of target data entries;
extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and
storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number of target data entries in the data segment.
18. The computer program product of claim 17, wherein the method further comprises referencing the intermediate cache line buffer rather than the main memory upon a target data entry fetch miss condition at the target data cache.
19. The computer program product of claim 17, wherein the method further comprises maintaining an address compare register containing an address of the data segment in the intermediate cache line buffer, the address compare register includes a bit selectively set to indicate whether the data segment stored in the intermediate cache line buffer is valid.
20. The computer program product of claim 17, wherein the plurality of target data entries comprises storage protection keys each associated with a chunk of data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A controller for a multiphase buck converter, configured to control a predetermined number of power stages defining an output voltage, the controller comprising:
a voltage supply input;
a control loop including a feedback voltage input configured to receive a feedback voltage proportional to output voltage;
a setpoint voltage input configured to receive a setpoint voltage that represents desired output voltage, the setpoint voltage including a DC error voltage;
circuitry configured to subtract the DC error voltage from the setpoint voltage to define a low voltage;
a ramp generator configured to generate a periodic repeating ramp signal that ramps from the low voltage to the feedback voltage then resets to the low voltage;
a phase clock coupled to the ramp generator and configured to generate a pulse each time the repeating ramp signal resets to the low voltage;
a phase counter coupled to the phase clock and configured to count each time a pulse is generated by the phase clock and to restart the count when the predetermined number is reached; and
a time on block having an input coupled to the phase counter and configured to turn on respective of the power stages when the counter is at predetermined count values;
wherein no PID compensator or compensated error amplifier is used in the control loop between the output voltage and the feedback voltage input.
2. A controller in accordance with claim 1 wherein the phase counter counts up.
3. A controller in accordance with claim 1 wherein the time on block is configured to turn on a first one of the power stages when the counter is at a value representing a count of 1 and to turn on a second one of the power stages when the counter is at a value representing a count of 2, and wherein the counter is configured to continue counting and turning on different ones of the power stages until the predetermined number is reached and then start again from 1.
4. A controller in accordance with claim 1 wherein the ramp generator reaches the feedback voltage more quickly when the feedback voltage drops.
5. A controller in accordance with claim 1 and including an adder configured to add the ramp signal to the low voltage to define a control signal output, wherein the phase clock is defined by a comparator configured to compare the control signal to the feedback voltage and to generate the phase clock pulse in response.
6. A controller for a multiphase buck converter, configured to control a predetermined number of power stages defining an output voltage, the controller comprising:
a voltage supply input;
a control loop including a feedback voltage input configured to receive a feedback voltage proportional to output voltage;
a setpoint voltage input configured to receive a setpoint voltage that represents desired output voltage; and
a ramp generator configured to generate a repeating ramp signal that ramps from a first voltage to the feedback voltage then resets to the first voltage, the ramp generator reaching the feedback voltage at faster intervals when the feedback voltage drops relative to the setpoint voltage, the power stages being turned on more frequently responsive to the ramp generator reaching the feedback voltage at faster intervals;
wherein no PID compensator or compensated error amplifier is used in the control loop between the output voltage and the feedback voltage input.
7. A multiphase buck converter including the controller of claim 6, and including power stages and respective inductances.
8. A multiphase buck converter in accordance with claim 7 and having no more than four output capacitors when the load line is about 0.75 mOhm.
9. A multiphase buck converter in accordance with claim 7 and further including a phase clock coupled to the ramp generator and configured to generate a pulse each time the repeating ramp signal resets to the low voltage.
10. A multiphase buck converter in accordance with claim 9 and further including a phase counter coupled to the phase clock and configured to count each time a pulse is generated by the phase clock and to restart the count when the counter has counted a number of times equal to the predetermined number of power stages.
11. A multiphase buck converter in accordance with claim 10 wherein the counter counts up starting from a value of one.
12. A computer including a processor and a memory coupled to the processor, the computer including the multiphase buck converter of claim 7 coupled to power the processor and the memory.
13. A vehicle having an engine, a battery, a sensor configured to sense an operating parameter of the engine, and an engine control computer coupled to the sensor and configured to adjust operation of the engine in response to the sensed parameter, the engine control computer including a processor and a memory coupled to the processor, the engine control computer including the multiphase buck converter of claim 7 coupled to receive power from the battery and coupled to supply power to the processor and the memory.
14. A method of controlling a multiphase buck converter configured to control a predetermined number of power stages defining an output voltage, the method comprising:
receiving an input voltage from a voltage supply;
receiving a feedback voltage signal, at a feedback voltage input, proportional to output voltage;
receiving a first voltage signal that represents desired output voltage;
generating a repeating ramp signal that ramps from a first voltage to the feedback voltage then resets to the first voltage, the ramp reaching the feedback voltage at faster intervals when the feedback voltage drops relative to the first voltage signal; and
turning on the power stages on more frequently responsive to the ramp generator reaching the feedback voltage at faster intervals;
wherein no PID compensator or compensated error amplifier is used between the output voltage and the feedback voltage input.
15. A method in accordance with claim 14 and further comprising generating a pulse each time the repeating ramp signal resets to the low voltage.
16. A method in accordance with claim 15 and further comprising counting each time a pulse is generated by the phase clock and restarting the count when the counter has counted a number of times equal to the predetermined number of power stages.
17. A method in accordance with claim 16 wherein the counting comprises counting up starting from a value of one.
18. A method in accordance with claim 14 and further comprising receiving an output current signal that represents output current, generating a load line signal proportional to output current, and subtracting the load line signal from a reference voltage signal indicative of desired voltage, to generate the first voltage signal.
19. A method in accordance with claim 14 wherein the load line signal and first voltage values are digital signals.
20. A method of computer comprising supplying power to a processor and to a memory using the method of claim 14.