1. An image processing circuit comprising:
a plurality of memories for storing line pixels of a frame constituting an image;
a specific pixel detecting unit for obtaining, for pixels of an arbitrary N\xd7N (N is a natural number) array of the frame of the image sequentially read from the plurality of memories, a luminance difference value which is a difference of luminance between an observation pixel positioned at a center of the array and each of other (N\xd7N\u22121) pixels, detecting a first minimum pixel (1) having a minimum luminance difference value among a plurality of pixels adjacent to the observation pixel, detecting a first minimum pixel (2) having a minimum luminance difference value from the observation pixel among three pixels opposite to the first minimum pixel (1) relative to the observation pixel, detecting a second minimum pixel (1) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (1), and detecting a second minimum pixel (2) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (2); and
a pixel interpolating unit for applying filter coefficients having predetermined weights to the observation pixel and specific pixels including the first minimum pixel (1), the first minimum pixel (2), the second minimum pixel (1) and the second minimum pixel (2) which are detected at the specific pixel detecting unit, applying filter coefficients having weights corresponding to the luminance difference value and a distance from the observation pixel to pixels other than the specific pixels in the N\xd7N pixels, obtaining a total sum of results of applying each filter coefficient to each pixel, and dividing the total sum by a total sum of filter coefficients of N\xd7N pixels to obtain an interpolated value for the observation pixel.
2. The image processing circuit according to claim 1, wherein the specific pixel detecting unit detects pixels from the first minimum pixel (1) and the first minimum pixel (2) to an M-th minimum pixel (1) to an M-th minimum pixel (2), where M (a natural number) is a quotient obtained by dividing N by 2, and in a case where the pixel is structured as the N\xd7N.
3. The image processing circuit according to claim 2, wherein the specific pixel detecting unit judges whether a luminance difference value between the observation pixel and the first minimum pixel (1) is not smaller than a predetermined isolated point removing threshold value, and if it is judged as not smaller than the isolated point removing threshold value, calculates an average value of luminance values of all pixels of the N\xd7N pixels to interpolate the observation pixel.
4. The image processing circuit according to claim 3, wherein; the pixel interpolating unit judges whether a luminance difference value between the first minimum pixel (1) and the first minimum pixel (2) is not smaller than a predetermined on-border erroneous interpolation removing threshold value, and if it is judged as not smaller than the on-border erroneous interpolation removing threshold value, sets the filter coefficients for the first minimum pixel (2) and the second minimum pixel (2) to \u201c0\u201d.
5. An imaging apparatus comprising:
an imaging unit for photographing an object and generating an image;
a plurality of memories for storing line pixels of a frame constituting the image generated by the imaging unit;
a specific pixel detecting unit for obtaining, for pixels of an arbitrary N\xd7N (N is a natural number) array of the frame of the image sequentially read from the plurality of memories, a luminance difference value which is a difference of luminance between an observation pixel positioned at a center of the array and each of other (N\xd7N\u22121) pixels, detecting a first minimum pixel (1) having a minimum luminance difference value among a plurality of pixels adjacent to the observation pixel, detecting a first minimum pixel (2) having a minimum luminance difference value from the observation pixel among three pixels opposite to the first minimum pixel (1) relative to the observation pixel, detecting a second minimum pixel (1) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (1), and detecting a second minimum pixel (2) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (2); and
a pixel interpolating unit for applying filter coefficients having predetermined weights to the observation pixel and specific pixels including the first minimum pixel (1), the first minimum pixel (2), the second minimum pixel (1) and the second minimum pixel (2) which are detected at the specific pixel detecting unit, applying filter coefficients having weights corresponding to the luminance difference value and a distance from the observation pixel to pixels other than the specific pixels in the N\xd7N pixels, obtaining a total sum of results of applying each filter coefficient to each pixel, and dividing the total sum by a total sum of filter coefficients of N\xd7N pixels to obtain an interpolated value for the observation pixel.
6. An image processing method comprising steps of:
for pixels of an arbitrary N\xd7N (N is a natural number) array of the frame constituting the image, obtaining a luminance difference value which is a difference of luminance between an observation pixel positioned at a center of the array and each of other (N\xd7N\u22121) pixels;
detecting a first minimum pixel (1) having a minimum luminance difference value among a plurality of pixels adjacent to the observation pixel;
detecting a first minimum pixel (2) having a minimum luminance difference value from the observation pixel among three pixels opposite to the first minimum pixel (1) relative to the observation pixel;
detecting a second minimum pixel (1) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (1);
detecting a second minimum pixel (2) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (2);
applying filter coefficients having predetermined weights to the observation pixel and specific pixels including the first minimum pixel (1), the first minimum pixel (2), the second minimum pixel (1) and the second minimum pixel (2), and applying filter coefficients having weights corresponding to the luminance difference value and a distance from the observation pixel to pixels other than the specific pixels in the N\xd7N pixels; and
obtaining a total sum of results of applying each filter coefficient to each pixel, and dividing the total sum by a total sum of filter coefficients of N\xd7N pixels to obtain an interpolated value for the observation pixel.
7. A program for causing a computer to execute image processing, the image processing comprising steps of
for pixels of an arbitrary N\xd7N (N is a natural number) array of the frame constituting the image, obtaining a luminance difference value which is a difference of luminance between an observation pixel positioned at a center of the array and each of other (N\xd7N\u22121) pixels;
detecting a first minimum pixel (1) having a minimum luminance difference value among a plurality of pixels adjacent to the observation pixel;
detecting a first minimum pixel (2) having a minimum luminance difference value from the observation pixel among three pixels opposite to the first minimum pixel (1) relative to the observation pixel;
detecting a second minimum pixel (1) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (1);
detecting a second minimum pixel (2) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (2);
applying filter coefficients having predetermined weights to the observation pixel and specific pixels including the first minimum pixel (1), the first minimum pixel (2), the second minimum pixel (1) and the second minimum pixel (2), and applying filter coefficients having weights corresponding to the luminance difference value and a distance from the observation pixel to pixels other than the specific pixels in the N\xd7N pixels; and
obtaining a total sum of results of applying each filter coefficient to each pixel, and dividing the total sum by a total sum of filter coefficients of N\xd7N pixels to obtain an interpolated value for the observation pixel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A layout structure of non-volatile memory device, comprising:
a semiconductor substrate having a plurality of isolation structures disposed therein and thereby a plurality of first transistor regions, a plurality of capacitor regions and a plurality of second transistor regions are defined in the semiconductor substrate, wherein each of the capacitor regions is disposed between corresponding first and second transistor regions in the Y-axis coordinate direction, and each two adjacent capacitor regions have corresponding first and second transistor regions arranged therebetween in the Y-axis coordinate direction;
a plurality of first-type doped wells disposed in the respective capacitor regions;
a plurality of first conductors arranged over the isolation structures, the first transistor regions and the first-type doped wells, wherein each of the first conductor comprises a first capacitor portion, a first transistor portion, a first edge and a second edge opposite to the first edge, the first capacitor portion is disposed over a corresponding first-type doped well, the first transistor portion is disposed over a corresponding first transistor region, the first edge is disposed over the isolation structure at a side of the corresponding first transistor region, and the second edge is disposed over the corresponding first-type doped well;
a plurality of second conductors arranged over the isolation structures, the second transistor regions and the first-type doped wells, wherein each of the second conductor comprises a second capacitor portion, a second transistor portion, a third edge and a fourth edge opposite to the third edge, the second capacitor portion is disposed over a corresponding first-type doped well, the second transistor portion is disposed over a corresponding second transistor region, the third edge is disposed over the isolation structure at a side of the corresponding second transistor region, and the fourth edge is disposed over the corresponding first-type doped well and adjacent to one of the second edges of the first conductors;
a plurality of first ion doped regions disposed in the respective first transistor regions at two sides of the first conductors, as well as disposed in the respective second transistor regions at two sides of the second conductors; the first ion doped regions constitute a plurality of first transistors cooperatively with the respective first transistor portions of the first conductors, as well as constitute a plurality of second transistors cooperatively with the respective second transistor portions of the second conductors; and
a plurality of second ion doped regions, wherein each of the second ion doped regions is disposed in the first-type doped well and between adjacent first conductor and second conductor, the second ion doped regions constitute a plurality of capacitors cooperatively with the respective first capacitor portions of the first conductors and second capacitor portions of the second conductors, each of the second ion doped regions acting as a control gate shared by a pair of two adjacent capacitors arranged in the Y-axis coordinate direction;
a plurality of word lines arranged on the semiconductor substrate, wherein the word lines are electrically coupled to the respective second ion doped regions; and
a plurality of bit lines arranged perpendicular to the word lines and on the semiconductor substrate, wherein the bit lines are electrically coupled to a part of the first ion doped regions respectively;
wherein each pair of two adjacent capacitors and corresponding first and second transistors sharing the same first and second conductors with the pair of two adjacent capacitors cooperatively constitute a pair of two adjacent non-volatile memory cells arranged in the Y-axis coordinate direction, and only one control gate and only one word line are shared between the two adjacent non-volatile memory cells arranged in the Y-axis coordinate direction.
2. The layout structure of non-volatile memory device as claimed in claim 1, wherein lengths of the first transistor portion and the first capacitor portion of each of the first conductors in the Y-axis coordinate direction are equal to each other.
3. The layout structure of non-volatile memory device as claimed in claim 1, wherein lengths of the first transistor portion and the first capacitor portion of each of the first conductors in the Y-axis coordinate direction are different from each other.
4. The layout structure of non-volatile memory device as claimed in claim 1, wherein lengths of the second transistor portion and the second capacitor portion of each of the second conductors in the Y-axis coordinate direction are equal to each other.
5. The layout structure of non-volatile memory device as claimed in claim 1, wherein lengths of the second transistor portion and the second capacitor portion of each of the second conductors in the Y-axis coordinate direction are different from each other.
6. The layout structure of non-volatile memory device as claimed in claim 1, wherein the semiconductor substrate is a second-type doped semiconductor substrate.
7. The layout structure of non-volatile memory device as claimed in claim 6, wherein the first-type doped wells are N-type doped wells, the first ion doped regions and the second ion doped regions are N-type ion doped regions, and the semiconductor substrate is a P-type semiconductor substrate.
8. The layout structure of non-volatile memory device as claimed in claim 1, further comprising a plurality of second-type doped wells sequentially arranged and discontinuously disposed in the respective first transistor regions and second transistor regions, and the first ion doped regions being disposed in the respective second-type doped wells.
9. The layout structure of non-volatile memory device as claimed in claim 8, wherein the first-type doped wells are N-type doped wells, the first ion doped regions and the second ion doped regions are N-type ion doped regions, and the second-type doped wells are P-type doped wells.
10. The layout structure of non-volatile memory device as claimed in claim 1, wherein lengths of the first capacitor portions and the second capacitor portions in the Y-axis coordinate direction are equal to each other.
11. The layout structure of non-volatile memory device as claimed in claim 10, wherein a width of each of the first-type doped wells in the Y-axis coordinate direction is larger than twice of the length of each of the first capacitor portions in the Y-axis coordinate direction.
12. A layout structure of non-volatile memory device, comprising:
a semiconductor substrate having a first transistor region, a common capacitor region and a second transistor region arranged in the Y-axis coordinate direction in that order and spaced from one another;
a first-type doped well disposed in the common capacitor region;
a plurality of first conductors arranged over the first transistor region and the first-type doped well, wherein each of the first conductors comprises a first edge and a second edge opposite to the first edge, the first edge is disposed at an outside of the first transistor region away from the first-type doped well, and the second edge is disposed directly above the first-type doped well;
a plurality of second conductors arranged over the second transistor region and the first-type doped well, wherein each of the second conductors comprises a third edge and a fourth edge opposite to the third edge, the third edge is disposed at an outside of the second transistor region away from the first-type doped well, and the fourth edge is disposed directly above the first-type doped well and adjacent to the second edge of one of the first conductors;
a plurality of first ion doped regions disposed in the first transistor region at two sides of the first conductors, as well as disposed in the second transistor region at two sides of the second conductors; the first ion doped regions constitute a plurality of first transistors cooperatively with the respective first conductors, as well as constitute a plurality of second transistors cooperatively with the respective second conductors; and
a second ion doped region, wherein the second ion doped region acts as a control gate shared by two of the first conductors and two of the second conductors, and the two first conductors and two second conductors are arranged surrounding the second ion doped region to thereby form two pairs of two adjacent capacitors arranged in the Y-axis coordinate direction;
a word line arranged on the semiconductor substrate and electrically coupled to the second ion doped region;
wherein each pair of two adjacent capacitors and corresponding first and second transistors sharing the same first and second conductors with the pair of two adjacent capacitors cooperatively constitute a pair of two adjacent non-volatile memory cells arranged in the Y-axis coordinate direction, only one control gate and only one word line are shared between the two adjacent non-volatile memory cells arranged in the Y-axis coordinate direction.
13. The layout structure of non-volatile memory device as claimed in claim 12, further comprising:
a plurality of bit lines arranged substantially perpendicular to the word line and on the semiconductor substrate, wherein the bit lines are electrically coupled to a part of the first ion doped regions respectively.
14. A layout structure of non-volatile memory device, comprising:
a semiconductor substrate;
a plurality of word lines arranged on the semiconductor substrate;
a plurality of ion doped regions disposed in the semiconductor substrate and each acting as a control gate electrically coupled with a corresponding one of the word lines;
a plurality of bit lines arranged substantially perpendicularly crossing over with the word lines on the semiconductor substrate and extending along the Y-axis coordinate direction;
a plurality of pairs of non-volatile memory cells arranged in the semiconductor substrate and electrically coupled to the respective word lines and bit lines,
wherein each pair of non-volatile memory cells comprise two adjacent non-volatile memory cells arranged in the Y-axis coordinate in which only one control gate and only one word line are shared between the two adjacent non-volatile memory cells arranged in the Y-axis coordinate direction.