What is claimed is:
1. A current reference circuit comprising:
a first MOS transistor having gate, drain, and source, wherein a gate voltage value is coupled from said gate to said source;
a second MOS transistor having gate, drain, and source, wherein said second MOS transistor is of the same size and type as said first said MOS transistor, wherein said source is coupled to said first MOS transistor source, and wherein said gate voltage value plus a delta voltage value is coupled from said gate to said source,
a means of forcing a drain voltage value from said drain to said source of said first MOS transistor and from said drain to said source of said second MOS transistor such that said first MOS transistor and said second MOS transistor conduct drain currents in the linear mode; and
a means of subtracting said first MOS transistor drain current from said second MOS transistor drain current to thereby create a current reference value wherein said current reference value does not depend upon the threshold voltage of said first and second MOS transistors.
2. The circuit according to claim 1 wherein said first and second MOS transistors comprise NMOS transistors.
3. The circuit according to claim 1 wherein said first and second MOS transistors comprise PMOS transistors.
4. The circuit according to claim 1 wherein said means of forcing a drain voltage value from said drain to said source of said first MOS transistor and from said drain to said source of said second MOS transistor comprises:
a first voltage follower comprising:
a first operational amplifier having positive input, negative input, and output, wherein said positive input is coupled to said drain voltage value and wherein said negative input is coupled to said first MOS transistor drain; and
a third MOS transistor having gate, drain, and source, wherein said gate is coupled to said first operational amplifier output and wherein said source is coupled to said first MOS transistor drain such that said drain voltage value is forced onto said first MOS transistor drain; and
a second voltage follower comprising:
a second operational amplifier having positive input, negative input, and output, wherein said positive input is coupled to said drain voltage value and wherein said negative input is coupled to said second MOS transistor drain; and
a fourth MOS transistor having gate, drain, and source, wherein said gate is coupled to said second operational amplifier output and wherein said source is coupled to said second MOS transistor drain such that said drain voltage value is forced onto said second MOS transistor drain.
5. The circuit according to claim 4 wherein said first, second, third, and fourth MOS transistors comprise NMOS transistors.
6. The circuit according to claim 4 wherein said first, second, third, and fourth MOS transistors comprise PMOS transistors.
7. The circuit according to claim 1 wherein said means of subtracting said first MOS transistor drain current from said second MOS transistor drain current to thereby create a delta current reference value comprises:
a fifth MOS transistor having gate, drain, and source, wherein said gate and said drain are coupled together and are further coupled to said first MOS transistor drain such that said fifth MOS transistor conducts a drain current equal to said first MOS transistor drain current;
a sixth MOS transistor having gate, drain, and source, wherein said source is coupled to said fifth MOS transistor source, wherein said drain is coupled to said second MOS transistor, and wherein said gate is coupled to said fifth MOS transistor gate such that said sixth MOS transistor conducts a drain current equal to said first MOS transistor drain current;
a seventh MOS transistor having gate, drain, and source, wherein said drain and said gate are coupled together and are further coupled to said second MOS transistor drain such that said seventh MOS transistor conducts a drain current equal to said second MOS transistor drain current minus said first MOS transistor drain current; and
an eighth MOS transistor having gate, drain, and source, wherein said source is coupled to said seventh MOS transistor source and wherein said gate is coupled to said seventh MOS transistor gate such that said eighth MOS transistor conducts a drain current equal to said seventh MOS transistor drain current.
8. The circuit according to claim 7 wherein said first and second MOS transistors comprise NMOS transistors and said fifth, sixth, seventh, and eighth MOS transistors comprise PMOS transistors.
9. The circuit according to claim 7 wherein said first and second MOS transistors comprise PMOS transistors and said fifth, sixth, seventh, and eighth MOS transistors comprise NMOS transistors.
10. A current reference circuit comprising:
a first MOS transistor having gate, drain, and source, wherein a gate voltage value is coupled from said gate to said source;
a second MOS transistor having gate, drain, and source, wherein said second MOS transistor is of the same size and type as said first said MOS transistor, wherein said source is coupled to said first MOS transistor source, and wherein said gate voltage value plus a delta voltage value is coupled from said gate to said source;
a means of forcing a drain voltage value from said drain to said source of said first MOS transistor and from said drain to said source of said second MOS transistor such that said first MOS transistor and said second MOS transistor conduct drain currents in the linear mode, said means of forcing comprising:
a first voltage follower comprising:
a first operational amplifier having positive input, negative input, and output, wherein said positive input is coupled to said drain voltage value and wherein said negative input is coupled to said first MOS transistor drain; and
a third MOS transistor having gate, drain, and source, wherein said gate is coupled to said first operational amplifier output and wherein said source is coupled to said first MOS transistor drain such that said drain voltage value is forced onto said first MOS transistor drain; and
a second voltage follower comprising:
a second operational amplifier having positive input, negative input, and output, wherein said positive input is coupled to said drain voltage value and wherein said negative input is coupled to said second MOS transistor drain; and
a fourth MOS transistor having gate, drain, and source, wherein said gate is coupled to said second operational amplifier output and wherein said source is coupled to said second MOS transistor drain such that said drain voltage value is forced onto said second MOS transistor drain; and
a means of subtracting said first MOS transistor drain current from said second MOS transistor drain current to thereby create a current reference value wherein said current reference value does not depend upon the threshold voltage of said first and second MOS transistors, said means of subtracting comprising:
a fifth MOS transistor having gate, drain, and source, wherein said gate and said drain are coupled together and are further coupled to said first MOS transistor drain such that said fifth MOS transistor conducts a drain current equal to said first MOS transistor drain current;
a sixth MOS transistor having gate, drain, and source, wherein said source is coupled to said fifth MOS transistor source, wherein said drain is coupled to said second MOS transistor, and wherein said gate is coupled to said fifth MOS transistor gate such that said sixth MOS transistor conducts a drain current equal to said first MOS transistor drain current;
a seventh MOS transistor having gate, drain, and source, wherein said drain and said gate are coupled together and are further coupled to said second MOS transistor drain such that said seventh MOS transistor conducts a drain current equal to said second MOS transistor drain current minus said first MOS transistor drain current; and
an eighth MOS transistor having gate, drain, and source, wherein said source is coupled to said seventh MOS transistor source and wherein said gate is coupled to said seventh MOS transistor gate such that said eighth MOS transistor conducts a drain current equal to said seventh MOS transistor drain current.
11. The circuit according to claim 10 wherein said first, second, third, and fourth MOS transistors comprise NMOS transistors and said fifth, sixth, seventh, and eighth MOS transistors comprise PMOS transistors.
12. The circuit according to claim 10 wherein said first, second, third, and fourth MOS transistors comprise PMOS transistors and said fifth, sixth, seventh, and eighth MOS transistors comprise NMOS transistors.
13. A nearly zero temperature coefficient current reference circuit comprising:
a positive temperature coefficient current reference circuit having inputs comprising a gate voltage value, a delta voltage value, and a drain voltage value, and having outputs comprising a current reference value, wherein said gate voltage value comprises a positive temperature coefficient value, wherein said delta voltage value comprises a positive temperature coefficient value, wherein said drain voltage value comprises a positive temperature coefficient value, and wherein said current reference value comprises a positive temperature coefficient current reference value; and
a negative coefficient current reference circuit having inputs comprising a gate voltage value, a delta voltage value, and a drain voltage value, and having outputs comprising a current reference value, wherein said gate voltage value comprises a negative temperature coefficient value, wherein said delta voltage value comprises a negative temperature coefficient value, wherein said drain voltage value comprises a positive temperature coefficient value, wherein said current reference value comprises a negative temperature coefficient current reference value, and wherein each of said positive temperature coefficient current reference circuit and said negative temperature coefficient current reference circuit comprises:
a first MOS transistor having gate, drain, and source, wherein a gate voltage value is coupled from said gate to said source;
a second MOS transistor having gate, drain, and source, wherein said second MOS transistor is of the same size and type as said first said MOS transistor, wherein said source is coupled to said first MOS transistor source, and wherein said gate voltage value plus a delta voltage value is coupled from said gate to said source,
a means of forcing drain voltage value from said drain to said source of said first MOS transistor and from said drain to said source of said second MOS transistor such that said first MOS transistor and said second MOS transistor conduct drain currents in the linear mode; and
a means of subtracting said first MOS transistor drain current from said second MOS transistor drain current to thereby create a current reference wherein said current reference does not depend upon the threshold voltage of said first and second MOS transistors; and
a means of adding said positive temperature coefficient current reference value to said negative temperature coefficient current reference value to thereby obtain a nearly zero temperature coefficient current reference.
14. The circuit according to claim 13 wherein said positive temperature coefficient value comprises a voltage proportional to the thermal voltage (VT).
15. The circuit according to claim 13 wherein said negative temperature coefficient value comprises a voltage proportional to the band gap voltage (VBG).
16. The circuit according to claim 13 wherein said first and second MOS transistors comprise NMOS transistors.
17. The circuit according to claim 13 wherein said means of forcing a drain voltage value from said drain to said source of said first MOS transistor and from said drain to said source of said second MOS transistor comprises:
a first voltage follower comprising:
a first operational amplifier having positive input, negative input, and output, wherein said positive input is coupled to said drain voltage value and wherein said negative input is coupled to said first MOS transistor drain; and
a third MOS transistor having gate, drain, and source, wherein said gate is coupled to said first operational amplifier output and wherein said source is coupled to said first MOS transistor drain such that said drain voltage value is forced onto said first MOS transistor drain; and
a second voltage follower comprising:
a second operational amplifier having positive input, negative input, and output, wherein said positive input is coupled to said drain voltage value and wherein said negative input is coupled to said second MOS transistor drain; and
a fourth MOS transistor having gate, drain, and source, wherein said gate is coupled to said second operational amplifier output and wherein said source is coupled to said second MOS transistor drain such that said drain voltage value is forced onto said second MOS transistor drain.
18. The circuit according to claim 13 wherein said means of subtracting said first MOS transistor drain current from said second MOS transistor drain current to thereby create a delta current reference value comprises:
a fifth MOS transistor having gate, drain, and source, wherein said gate and said drain are coupled together and are further coupled to said first MOS transistor drain such that said fifth MOS transistor conducts a drain current equal to said first MOS transistor drain current;
a sixth MOS transistor having gate, drain, and source, wherein said source is coupled to said fifth MOS transistor source, wherein said drain is coupled to said second MOS transistor, and wherein said gate is coupled to said fifth MOS transistor gate such that said sixth MOS transistor conducts a drain current equal to said first MOS transistor drain current;
a seventh MOS transistor having gate, drain, and source, wherein said drain and said gate are coupled together and are further coupled to said second MOS transistor drain such that said seventh MOS transistor conducts a drain current equal to said second MOS transistor drain current minus said first MOS transistor drain current; and
an eighth MOS transistor having gate, drain, and source, wherein said source is coupled to said seventh MOS transistor source and wherein said gate is coupled to said seventh MOS transistor gate such that said eighth MOS transistor conducts a drain current equal to said seventh MOS transistor drain current.
19. The circuit according to claim 18 wherein said first and second MOS transistors comprise NMOS transistors and said fifth, sixth, seventh, and eighth MOS transistors comprise PMOS transistors.
20. The circuit according to claim 18 wherein said first and second MOS transistors comprise PMOS transistors and said fifth, sixth, seventh, and eighth MOS transistors comprise NMOS transistors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An optical apparatus comprising:
a first member; and
a second member for rotating around an optical axis with respect to the first member, wherein:
one of the first member and the second member has a cam portion;
the other of the first member and the second member has a cam follower portion for being engaged with the cam portion;
the cam portion drives the first member and the second member relatively to each other in an optical axis direction through relative rotation of the first member and the second member;
the first member has first protruding portions and second protruding portions which protrude toward the second member side at positions separate from each other in the optical axis direction;
the second member has third protruding portions and fourth protruding portions which protrude toward the first member side at positions separate from each other in the optical axis direction and can abut on the first protruding portions and the second protruding portions in the optical axis direction, respectively; and
the fourth protruding portions are provided in a circumferential direction of the second member and include protruding portions for transmitting a power.
2. An optical apparatus according to claim 1, wherein the second protruding portions can abut on the fourth protruding portions when at least the first member and the second member are located at relative rotational positions so that a portion of the third protruding portions which is shorter than an entire length of the third protruding portions in the circumferential direction can abut on the first protruding portions.
3. An optical apparatus according to claim 1, wherein object side surfaces of the first protruding portions and the second protruding portions can abut on image plane side surfaces of the third protruding portions and the fourth protruding portions, respectively, when the second member has been driven toward the object side with respect to the first member.
4. An optical apparatus according to claim 1, wherein the fourth protruding portions include a gear portion for receiving a driving force for rotationally driving the second member.
5. An optical apparatus according to claim 1, wherein the fourth protruding portions include protruding portions for transmitting rotation of the second member to another member.
6. An optical apparatus according to claim 1, wherein:
the cam portion is formed so that the cam portion drives the first member and the second member relatively to each other in the optical axis direction when the first member and the second member rotate relatively to each other in a first rotational range, and stops driving the first member and the second member relatively to each other in the optical axis direction when the first member and the second member rotate relatively to each other in a second rotational range; and
the first protruding portions and the second protruding portions can abut on the third protruding portions and the fourth protruding portions, respectively, when the first member and the second member are in the second rotational range.
7. An optical apparatus according to claim 1, wherein the first protruding portions and the second protruding portions are provided outside moving ranges of the third protruding portions and the fourth protruding portions, respectively, at a time when the second member is driven with respect to the first member in the optical axis direction.
8. An optical apparatus according to claim 1, wherein the second protruding portions close an opening formed in another member that is adjacent to the first member in a direction perpendicular to the optical axis.
9. An optical apparatus comprising:
a first member; and
a second member for rotating around an optical axis with respect to the first member, wherein:
one of the first member and the second member has a cam portion;
the other of the first member and the second member has a cam follower portion for being engaged with the cam portion;
the cam portion drives the first member and the second member relatively to each other in the optical axis direction through relative rotation of the first member and the second member;
the first member is provided with protruding portions for the first member which protrudes toward the second member side;
the second member is provided with protruding portions for the second member which protrude toward the first member side and can abut on the protruding portions for the first member from the optical axis direction; and
the protruding portions for the second member are provided in a circumferential direction of the second member and include protruding portions for transmitting power.
10. An optical apparatus according to claim 9, further comprising a photoelectric conversion element for performing photoelectric conversion of an object image formed by an optical system including a lens.