What is claimed is:
1 A buffer using a two-port memory, comprising:
a memory cell array formed of memory cells arranged two-dimensionally in a matrix form;
a plurality of write-word lines arranged corresponding to a write address;
a plurality of read-word lines arranged corresponding to a read address;
a plurality of write bit lines arranged corresponding to write data;
a plurality of read bit lines arranged corresponding to read data;
a plurality of word line registers arranged corresponding to either said write word lines or said read word lines;
a plurality of word line drivers respectively connected directly to outputs of said word line registers, for respectively driving said word lines;
a write data register connected to said write bit lines; and
a read data register connected to said read bit line;
said word line registers being mutually cascaded in a ring form, to receive a strobe signal;
whereby each of said word line registers counts up its input when the strobe signal is in an active state and holds a current value when said strobe signal is not in an active state.
2 A buffer using a two-port memory, comprising:
a memory cell array formed of memory cells arranged two-dimensionally in a matrix form;
a plurality of write-word lines arranged corresponding to a write address;
a plurality of read-word lines arranged corresponding to a read address;
a plurality of write bit lines arranged corresponding to write data;
a plurality of read bit lines arranged corresponding to read data;
a plurality of write word line registers arranged corresponding to said write word lines;
a plurality of read word line registers arranged corresponding to said read word lines;
a plurality of write word line drivers for directly receiving outputs of said write word line registers, for driving said write word lines;
a plurality of read word line drivers for directly receiving outputs of said read word line registers and driving said read word lines;
a write data register connected to said write bit lines; and
a read data register connected to said read bit line; said write word line registers being mutually cascaded in a ring form, to receive a write strobe signal;
whereby each of said write word line registers counts up an input when the write strobe signal is in an active state and holds a current value when said write strobe signal is not in an active state;
said read word line registers being mutually cascaded in a ring form, to receive a read strobe signal;
whereby each of said read word line registers counts up an input when the read strobe signal is in an active state and holds a current value when said read strobe signal is not in an active state.
3 The buffer defined in claim 2, wherein said write strobe signal is used to controllably update said write data register; and wherein said read strobe signal is used to controllably update said read data register; and wherein said write data register updates write data when said write strobe signal is in an active state; and wherein said read data register updates read data when said read strobe signal is in an active state; and wherein said write data register hold a current value when said write strobe signal is not in an active state; and wherein said read data register hold a current value when said read strobe signal is not in an active state.
4 The buffer defined in claim 3, wherein a write word line register corresponding to a specific address receives a write START signal as a synchronous set input; and wherein a read word line register corresponding to a specific address receives a read START signal as a synchronous set input.
5 The buffer defined in claim 3, further comprising:
a write address initial value register for storing a write address initial value;
a write address initial value decoder for decoding a write address initial value stored in said write address initial value register;
a plurality of AND logic circuits for creating a synchronous set signal to said write word line register in accordance with plural decode addresses from said write address initial value decoder and in accordance with a write START signal;
a read address initial value register for storing a read address initial value;
a read address initial value decoder for decoding a read address initial value stored in said read address initial value register; and
a plurality of AND logic circuits for creating a synchronous set signal to said read word line register in accordance with plural decode addresses from said read address initial value decoder and in accordance with a read START signal.
6 The buffer defined in claim 5, further comprising:
a write delay register, which forms a leading edge differentiation circuit, for detecting rising when a write word line register of a most significant address is in an active state and then creating one clock pulse;
an AND logic circuit with write negative inputs, having an inversion input terminal which receives an output of said write delay register and a normal input terminal which receives an output of said write word line register of said most significant address;
a write exclusive OR logic circuit forming a write address carry flag for toggling one clock pulse as an input;
a write flag register for receiving an output of said write exclusive OR logic circuit;
a read delay register forming a leading edge differentiation circuit that detects rising when a read word line register of the most significant address becomes an active state and then creates one clock pulse;
an AND logic circuit with read negative inputs, having an inversion input terminal for receiving an output of said read delay register and a normal input terminal for receiving an output of said read word line register of the most significant address;
a read exclusive OR logic circuit forming a read address carry flag toggling one clock pulse as an input;
a read flag register for receiving an output of said read exclusive OR logic circuit;
a plurality of coincidence detection AND logic circuits each for detecting whether or not a value held in each write word line register coincides with a value held in each read word line register;
an OR logic circuit for detecting whether or not there is a coincidence result in any one of said coincidence detection AND logic circuit;
an exclusive OR logic circuit and an AND logic circuit, for detecting a buffer overflow when a write address carry flag is not in coincident with a read address carry flag and when said OR logic circuit produces a coincidence result; and
an exclusive NOR logic circuit and an AND logic circuit, for detecting a buffer underflow when a write address carry flag is in coincident with a read address carry flag and when said OR logic circuit produces a coincidence result.
7 The buffer defined in claim 2, wherein a write word line register corresponding to a specific address receives a write START signal as a synchronous set input; and wherein a read word line register corresponding to a specific address receives a read START signal as a synchronous set input.
8 The buffer defined in claim 2, further comprising:
a write address initial value register for storing a write address initial value;
a write address initial value decoder for decoding a write address initial value stored in said write address initial value register;
a plurality of AND logic circuits for creating a synchronous set signal to said write word line register in accordance with plural decode addresses from said write address initial value decoder and in accordance with a write START signal;
a read address initial value register for storing a read address initial value;
a read address initial value decoder for decoding a read address initial value stored in said read address initial value register; and
a plurality of AND logic circuits for creating a synchronous set signal to said read word line register in accordance with plural decode addresses from said read address initial value decoder and in accordance with a read START signal.
9 A buffer using a two-port memory, comprising: a memory cell array formed of memory cells arranged two-dimensionally in a matrix form;
a plurality of write word lines arranged corresponding to a write address;
a plurality of read word lines arranged corresponding to a read address;
a plurality of write bit lines arranged corresponding to write data;
a plurality of read bit lines arranged corresponding to read data;
a plurality of write word line registers arranged corresponding to said write word lines, for counting up an input based on a write strobe signal;
a plurality of read word line registers arranged corresponding to said read word lines, for counting up an input based on a read strobe signal;
a plurality of write word line drivers for driving said write word lines based on output signals from said write word line registers;
a plurality of read word line drivers for driving said read word lines based on output signals from said read word line registers;
a write data register for updating write data when said write strobe signal is active and for holding a current value when said write strobe signal is not active; and
a read data register for updating read data when said read strobe signal is active and for holding a current value when said read strobe signal is not active.
10 The buffer defined in claim 9, wherein a write word line register corresponding to a predetermined address receives a write START signal as a synchronous set input; and wherein a read word line register corresponding to a predetermined address receives a read START signal as a synchronous set input.
11 The buffer defined in claim 9, further comprising:
a write address initial value register for storing a write address initial value;
a write address initial value decoder for decoding a write address initial value stored in said write address initial value register;
a plurality of AND logic circuits for creating a synchronous set signal to said write word line register in accordance with a signal from said write address initial value decoder and in accordance with a write START signal;
a read address initial value register for storing a read address initial value;
a read address initial value decoder for decoding a read address initial value stored in said read address initial value register; and
a plurality of AND logic circuits for creating a synchronous set signal to said read word line register in accordance with a signal from said read address initial value decoder and in accordance with a read START signal.
12 The buffer defined in claim 9, further comprising:
a clock pulse creation circuit in the write system, for detecting rising when a write word line register of a most significant address becomes an active state and then creating one clock pulse;
a write exclusive OR logic circuit for creating a write address carry flag based on one clock pulse created by said clock pulse creation circuit in the write system;
a write flag register for receiving an output signal of said write exclusive OR logic circuit;
a clock pulse creation circuit in the read system, for detecting rising when a read word line register of the most significant address becomes an active state and then creating one clock pulse;
a read exclusive OR logic circuit for creating a read address carry flag based on one clock pulse created by said clock pulse creation circuit in the read system;
a read flag register for receiving an output signal of said read exclusive OR logic circuit;
a plurality of coincidence detection AND logic circuits for detecting whether or not a value held in each write word line register coincides with a value held in each read word line register;
an OR logic circuit for detecting whether or not there is a coincidence result in any one of said coincidence detection AND logic circuit;
an exclusive OR logic circuit and an AND logic circuit, for detecting a buffer overflow when a write address carry flag is not in coincident with a read address carry flag and when said OR logic circuit produces a coincidence result; and
an exclusive NOR logic circuit and an AND logic circuit, for detecting a buffer underflow when a write address carry flag is in coincident with a read address carry flag and when said OR logic circuit produces a coincidence result.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer-implemented method of enabling programmatic management of software resources in a content aggregation framework environment, comprising steps of:
providing a system management interface for a proxying component, wherein the proxying component enables operations invocable from one or more software resources in a collection to be invocable from a content aggregation framework and the system management interface enables the software resources in the collection to be managed from the content aggregation framework, the system management interface specifying management operations invocable from the collection as management operations invocable from the proxying component;
specifying the system management interface in a service description document; and
registering the service description document in a network-accessible registry, such that the system management interface of the proxying component is locatable from the network-accessible registry.
2. The method according to claim 1, further comprising the step of using the system management interface at run-time to manage the collection of software resources by invoking, from the content aggregation framework, one or more of the management operations invocable from the system management interface of the proxying component, wherein each of the invocations causes the proxying component to invoke a corresponding management operation that is invocable from the collection of software resources.
3. The method according to claim 2, wherein the using step further comprises the steps of:
retrieving, by the content aggregation framework, the registered service description document for the proxying component from the network-accessible registry;
binding, by content aggregation framework, to the system management interface of the proxying component using the retrieved service description document, such that the operations invocable from the system management interface of the proxying component are then invocable from the content aggregation framework.
4-5. (canceled)
6. The method according to claim 2, wherein at least one of the invoked management operations is a life cycle event implemented by one of the software resources in the collection.
7-11. (canceled)
12. The method according to claim 1, wherein the proxying component is a portlet.
13. The method according to claim 1, wherein the content aggregation framework is a portal platform.
14. The method according to claim 1, wherein the collection comprises a web service.
15. A system for enabling programmatic management of software resources in a content aggregation framework environment, comprising:
a content aggregation framework adapted for supporting one or more plug-in components, each of which contributes content for aggregating in the content aggregation framework;
a collection of software resources, each having one or more invocable operations;
a proxying component structured as one of the plug-in components;
means for using the proxying component to surface the invocable operations of the collection of software resources in the content aggregation framework by specifying, for the proxying component, a functional interface in which selected ones of the invocable operations are surfaced as invocable operations of the proxying component;
means for using the proxying component to manage the collection of software resources by specifying, for the proxying component, a system management interface in which other selected ones of the invocable operations are surfaced as invocable management operations of the proxying component, the other selected ones providing management operations that are invocable from the collection of software resources;
means for specifying, for the proxying component, the functional interface and the system interface in a service description document; and
means for registering, for the proxying component, the service description document in a network-accessible registry, such that the proxying component can be located at run-time by searching the network-accessible registry and then plugged in to the content aggregation framework, thereby surfacing the selected invocable operations and the other selected invocable operations for invocation from the content aggregation framework, via the plugged-in proxying component.
16. The system according to claim 15, further comprising means for using the system management interface at run-time to manage the collection of software resources by invoking, from the content aggregation framework, one or more of the other selected invocable operations surfaced therein, wherein each of the invocations causes the plugged-in proxying component to invoke a corresponding one of the management operations that is invocable from the collection of software resources.
17. The system according to claim 16, wherein the means for using the system management interface further comprises:
means for retrieving, by the content aggregation framework, the registered service description document of the proxying component from the network-accessible registry; and
means for binding, by the content aggregation framework, to the system management interface of the proxying component using the system management interface specified in the retrieved service description document, thereby causing the other selected invocable operations to become invocable from the content aggregation framework.
18. (canceled)
19. The system according to claim 15, further comprising means for using 2-way communications to initiate communication of auditing information from one or more of the software resources, via the plugged-in proxying component, to the content aggregation framework, wherein the auditing information comprises at least one of (1) quality of service information from one or more of the software resources, (2) billing information from one or more of the software resources, (3) notification of one or more events occurring at one or more of the software resources, and (4) operational messages from one or more of the software resources.
20. The system according to claim 15, wherein the collection comprises a web service and the proxying component is a portlet, and wherein the content aggregation framework is a portal platform.
21. A computer program product for enabling programmatic management of software resources in a content aggregation framework environment, the computer program product embodied on one or more computer-readable media and comprising:
computer-readable program code for specifying, in a service description document, a system management interface for a proxying component, wherein the proxying component is adapted for plugging in to a content aggregation framework and serves, when plugged in to the content aggregation framework, as a proxy for a collection of one or more software resources that are thereby accessible from the content aggregation framework, and wherein the system management interface specifies management operations that are invocable from the collection of software resources as management operations that are invocable from the plugged-in component;
computer-readable program code for registering the service description document in a network-accessible registry;
computer-readable program code for using the registered service description document to locate the proxying component when searching the network-accessible registry;
computer-readable program code for plugging the located proxying component in to the content aggregation framework; and
computer-readable program code for managing the software resources from the content aggregation framework, via the plugged-in proxying component, by invoking one or more of the management operations that are invocable from the plugged-in proxying component.
22. The computer program product according to claim 21, wherein each of the one or more invocations causes the plugged-in proxying component to invoke a corresponding one of the management operations that are invocable from the collection of software resources.
23. The computer program product according to claim 21, wherein the computer-readable program code for plugging the located proxying component in to the content aggregation framework further comprises
computer-readable program code for binding, by content aggregation framework, to the system management interface of the located proxying component using the system management interface specified in the registered service description document.
24. (canceled)
25. The computer program product according to claim 21, further comprising computer-readable program code for using 2-way communications to initiate communication of auditing information from one or more of the software resources, via the plugged-in proxying component, to the content aggregation framework, wherein the auditing information comprises at least one of (1) quality of service information from one or more of the software resources, (2) billing information from one or more of the software resources, (3) notification of one or more events occurring at one or more of the software resources, the event notification for logging by the content aggregation framework, and (4) operational messages from one or more of the software resources.
26. The computer program product according to claim 21, wherein the collection comprises a web service and the proxying component is a portlet, and wherein the content aggregation framework is a portal platform.