1. An active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, each pixel comprising:
an electroluminescent (EL) display element;
a drive transistor for driving a current through the display element;
means for directly interrupting the drive of current through the display element via a direct interrupt signal, said direct interruption means being provided in series with the electroluminescent display element; and
row driver circuitry for generating control voltages to be applied to the pixels in each row in sequence including a drive voltage as input to the interrupting means,
wherein the row driver circuitry comprises a shift register arrangement and logic arrangement for generating the drive voltage for the interrupting means, the drive voltage for the interrupting means including a long emission time pulse for controlling the output of the display element, the long emission time pulse having a duration which can be varied up to substantially the full field period less the address period, and wherein the timing of the end of the long emission time pulse corresponds to the timing of the direct interrupt signal generated by the interrupting means for controlling the display element illumination time,
wherein the signal or signals propagated through the shift register arrangement control the pulse duration.
2. A device as claimed in claim 1, wherein the shift register arrangement and logic arrangement comprises first and second shift register devices, each having a pulse propagating through them, and logic means for deriving a signal having a pulse with duration derived from the difference in timing of the pulses propagating through the first and second shift register devices.
3. A device as claimed in claim 1, wherein the pulse propagating in each shift register device has a duration corresponding the line time of the display.
4. A device as claimed in claim 1, wherein the logic means comprises a transmission gate which transmits a low pulse in response to a pulse on one of the shift register devices and transmits a high pulse in response to a pulse on the other one of the shift register devices.
5. A device as claimed in claim 4, wherein the logic means further comprises a memory cell for maintaining a constant output between pulses received from the transmission gate.
6. A device as claimed in claim 1, wherein the shift register arrangement and logic arrangement comprises first and second shift register devices, each having a pulse propagating through them, and logic means for deriving a signal having a pulse with duration derived from the duration of the pulse in one of the first and second shift register devices.
7. A device as claimed in claim 6, wherein the pulse propagating in one shift register device has a duration corresponding to the line time of the display and the pulse propagating in the other shift register device has a duration for controlling the display element illumination period.
8. A device as claimed in claim 1, wherein the shift register arrangement and logic arrangement comprises a shift register device, having a pulse propagating through it having a duration dependent on the desired illumination time of the display element, and logic means for deriving from the shift register device a pulse having a duration corresponding to the line time of the display.
9. A device as claimed in claim 8, wherein the logic means for deriving from the shift register device a pulse having a duration corresponding to the line time of the display comprises a combination element for combining the pulse at the output of one shift register element (n) for one row with the pulse at the output of another shift register element (n+1) for an adjacent row.
10. A device as claimed in claim 1, wherein each pixel comprises drive transistor threshold compensation circuitry.
11. A device as claimed in claim 10, wherein the drive transistor, the electroluminescent display element and means for interrupting the drive of current through the display element are connected in series between a power supply line and a common potential line.
12. A device as claimed in claim 11, wherein the means for interrupting comprises a transistor.
13. An active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, each pixel comprising:
an electroluminescent (EL) display element;
a drive transistor for driving a current through the display element;
means for interrupting the drive of current through the display element; and
row driver circuitry for generating control voltages to be applied to the pixels in each row in sequence including a drive voltage for the interrupting means,
wherein the row driver circuitry comprises a shift register arrangement and logic arrangement for generating the drive voltage for the interrupting means, the drive voltage for the interrupting means including a pulse having a duration which can be varied up to substantially the full field period less the address period,
wherein the signal or signals propagated through the shift register arrangement controls the pulse duration,
wherein a first pulse from the shift register arrangement and logic arrangement is combined with a first template control signal or signals (A1, A2) to provide a first control signal or signals (A1r,A2r) for the addressing of the pixel, and a second pulse from the shift register arrangement and logic arrangement is combined with a second template control signal (A3) to provide the drive voltage (A3r) for the interrupting means both during the addressing of the pixel and during subsequent driving of the pixel.
14. A device as claimed in claim 13, wherein the first pulse has duration equal to the line time.
15. A device as claimed in claim 13, wherein the second pulse has duration selected to control the display element illumination time.
16. An active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, each pixel comprising:
an electroluminescent (EL) display element;
a drive transistor for driving a current through the display element; means for interrupting the drive of current through the display element; and
row driver circuitry for generating control voltages to be applied to the pixels in each row in sequence including a drive voltage for the interrupting means,
wherein the row driver circuitry comprises a shift register arrangement and logic arrangement for generating the drive voltage for the interrupting means, the drive voltage for the interrupting means including a pulse having a duration which can be varied up to substantially the full field period less the address period,
wherein the signal or signals propagated through the shift register arrangement controls the pulse duration,
wherein each pixel comprises drive transistor threshold compensation circuitry,
wherein the drive transistor threshold compensation circuitry comprises first and second capacitors connected in series between the gate and source of the drive transistor, a data input to the pixel being provided to the junction between the first and second capacitors thereby to charge the first capacitor to a voltage derived from the pixel data voltage, and a voltage derived from the drive transistor threshold voltage being stored on the second capacitor.
17. A method of driving an active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, in which each pixel comprises an electroluminescent (EL) display element, a drive transistor for driving a current through the display element and means for directly interrupting the drive of current through the display element provided in series with the electroluminescent display element, the method comprising:
propagating a pulse or pulses through a shift register arrangement;
using a pulse from the shift register arrangement to allow pixel addressing control voltages to be applied to the pixels of a row during an addressing period;
using the shift register pulse or pulses to derive a drive voltage as input to the interrupting means including a long emission time pulse for controlling the output of the display element, the long emission time pulse having a duration which can be varied up to substantially the full field period less the addressing period; and
applying the drive voltage for the interrupting means to the interrupting means after the pixel addressing period, the timing of the end of the pulse corresponding to the timing of an interrupt by the means for interrupting,
wherein the shift register arrangement and logic arrangement comprises first and second shift register devices, each having a pulse propagating through them, and logic means for deriving a signal having a long emission time pulse derived from the difference in timing of the pulses propagating through the first and second shift register devices, and
wherein said derived signal is synchronized to the frame time.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory system comprising:
a substrate;
a plurality of memory chips mounted over the substrate, the plurality of memory chips receiving a first signal and a second signal;
a memory buffer mounted over the substrate, the memory buffer including a detection circuit which detects a skew between the first signal and the second signal, and the memory buffer including an adjustment circuit which adjusts a relationship between the first signal and the second signal based on the skew.
a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common; and
a plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips.
2. The memory system according to claim 1, wherein each second end of the plurality of second wirings is configured to couple to the memory buffer.
3. The memory system according to claim 1, wherein the first signal is a clock signal or a commandaddress signal, the second signal includes a date signal or a timing signal being synchronized with the date signal.
4. The memory system according to claim 1, further comprising an output circuit supplying a third signal based on the first signal or the second signal from each of the plurality of the memory chips to a memory controller.
5. The memory system according to claim 1, wherein selected one of the plurality of memory chips based on the first and second signals outputs a third signal and a fourth signal to the memory buffer chip, the detection circuit in the memory buffer chip which detects a skew between the third and fourth signals, and an adjustment circuit in the memory buffer chip which adjust a relationship between the third signal and the fourth signal based on the skew.
6. The memory system according to claim 1, wherein the plurality of memory chips includes a first plurality of memory chips mounted over a first area of the substrate and a second plurality of memory chips mounted over a second area of the substrate, and the memory buffer chip mounted over a third area of the substrate between the first area and the second area.
7. The memory system according to claim 1, wherein the memory buffer chip receives commandaddress signals and data signals from a memory controller, and outputs the first signal based on the commandaddress signals and the second signal based on the data signals.
8. The memory module according to claim 2, wherein the first signal is a clock signal or a commandaddress signal, the second signal include a date signal or a timing signal being synchronized with the date signal.
9. The memory module according to claim 1, further comprising an output circuit supplying a third signal based on the first signal or the second signal.
10. A memory system comprising:
a substrate;
a plurality of memory chips mounted over the substrate; the plurality of memory chips receiving a first signal and a second signal;
a memory buffer mounted over the substrate;
a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common;
a plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips, each second end of the plurality of second wirings is configured to couple to the memory buffer; and
a memory controller coupled to the memory buffer and supplying the memory buffer with a plurality of signals, the memory buffer generating the first signal and the second signal based on the plurality of signals;
wherein at least one of the memory buffer and the memory controller includes a detection circuit which detects a skew between the first signal and the second signal and an adjustment circuit which adjust a relationship between the first signal and the second signal based on the skew.
11. The memory system according to claim 10, wherein the first signal is a signal based on a clock signal or a commandaddress signal supplied from the memory controller as a part of the plurality of signals, the second signal is a date signal or a timing signal being synchronized with the date signal supplied from the memory controller as a part of the plurality of signals.
12. The memory system according to claim 10, wherein each of the memory controller and the memory buffer includes a detection circuit which detects a skew between the first signal and the second signal and an adjustment circuit which adjust a relationship between the first signal and the second signal based on the skew.
13. A memory system comprising:
a substrate;
a plurality of memory chips mounted over the substrate; the plurality of memory chips receiving a first signal and a second signal;
a memory buffer mounted over the substrate;
a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common;
a plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips, each second end of the plurality of second wirings is configured to couple to the memory buffer; and
a memory controller coupled to the memory buffer and supplying the memory buffer with a plurality of signals, the memory buffer generating the first signal and the second signal based on the plurality of signals;
wherein each of the memory buffer and the memory controller includes a detection circuit which detects a skew between the first signal and the second signal and an adjustment circuit which adjust a relationship between the first signal and the second signal based on the skew.
14. The memory system according to claim 13, wherein the first signal is a signal based on a clock signal or a commandaddress signal supplied from the memory controller as a part of the plurality of signals, the second signal is a date signal or a timing signal being synchronized with the date signal supplied from the memory controller as a part of the plurality of signals.