1. A memory circuit comprising:
a plurality of memory cells, organized into columns and rows, that are accessed during memory access cycles, which include refresh cycles and readwrite cycles, wherein the memory cells are substantially continuously refreshed using the refresh cycles;
a plurality of sense amplifiers, wherein each said sense amplifier is coupled to a corresponding one of the columns of the memory cells, and is used to read data stored in the memory cells of the corresponding column during read phases of the refresh cycles and the readwrite cycles; and
a plurality of write amplifiers, wherein each said write amplifier is coupled to a corresponding one of the columns of the memory cells of the corresponding column, and is used to write data to the memory cells during write phases of the memory access cycles,
wherein the read phases of the refresh cycles substantially coincide with the write phases of the readwrite cycles, and the write phases of the refresh cycles substantially coincide with the read phases of the readwrite cycles.
2. The memory circuit of claim 1, further comprising a readwrite address generator for generating read and write addresses.
3. The memory circuit of claim 2, further comprising a refresh address generator for generating refresh addresses used to refresh the memory cells.
4. The memory circuit of claim 3, further comprising a collision avoidance mechanism, which prevents an attempt to perform both refresh and readwrite operations concurrently on identical said memory cells.
5. The memory circuit of claim 4, wherein the collision avoidance mechanism compares the refresh addresses with the readwrite addresses to determine whether the attempt is made to perform both the refresh and readwrite operations concurrently on the identical said memory cells.
6. The memory circuit of claim 5, wherein at least one of the refresh addresses is updated to prevent the attempt to perform both the refresh and readwrite operations concurrently on the identical said memory cells.
7. The memory circuit of claim 6, wherein the at least one of the refresh addresses is updated by being changed by at least one.
8. A method of refreshing memory cells organized into columns and rows, the memory cells being accessed during memory access cycles, which include refresh cycles and readwrite cycles, the method comprising:
reading data stored in the memory cells during read phases of the memory access cycles, wherein same sense amplifiers are used to read the memory cells during both the refresh cycles and the readwrite cycles; and
writing data to the memory cells during write phases of the memory access cycles,
wherein the memory cells are substantially continuously refreshed, and
wherein the read phases of the refresh cycles substantially coincide with the write phases of the readwrite cycles, and the write phases of the refresh cycles substantially coincide with the read phases of the readwrite cycles.
9. The method of claim 8, further comprising generating read and write addresses.
10. The method of claim 9, further comprising generating refresh addresses used to refresh the memory cells.
11. The method of claim 10, further comprising preventing an attempt to perform both refresh and readwrite operations concurrently on identical said memory cells.
12. The method of claim 11, wherein preventing comprises comparing the refresh addresses with the readwrite addresses to determine whether the attempt is made to perform both the refresh and readwrite operations concurrently on the identical said memory cells.
13. The method of claim 12, wherein preventing further comprises updating at least one of the refresh addresses to prevent the attempt to perform both the refresh and readwrite operations concurrently on the identical said memory cells.
14. The method of claim 13, wherein updating comprises changing the at least one of the refresh addresses by at least one.
15. A system-on-chip (SOC) device comprising:
data processing circuitry for processing input data to generate output data;
an IO port for receiving the input data and for outputting the output data; and
a memory block comprising:
a plurality of memory cells, organized into columns and rows, that are accessed during memory access cycles, which include refresh cycles and readwrite cycles, wherein the memory cells are substantially continuously refreshed using the refresh cycles;
a plurality of sense amplifiers, wherein each said sense amplifier is coupled to a corresponding one of the columns of the memory cells, and is used to read data stored in the memory cells of the corresponding column during read phases of the refresh cycles and the readwrite cycles, wherein the data processing circuitry processes the input data based on the data stored in the memory cells to generate the output data; and
a plurality of write amplifiers, wherein each said write amplifier is coupled to a corresponding one of the columns of the memory cells of the corresponding column, and is used to write data to the memory cells during write phases of the memory access cycles,
wherein the read phases of the refresh cycles substantially coincide with the write phases of the readwrite cycles, and the write phases of the refresh cycles substantially coincide with the read phases of the readwrite cycles.
16. The SOC device of claim 15, wherein the memory block further comprises a readwrite address generator for generating read and write addresses.
17. The SOC device of claim 16, wherein the memory block further comprises a refresh address generator for generating refresh addresses used to refresh the memory cells.
18. The SOC device of claim 17, wherein the memory block further comprises a collision avoidance mechanism, which prevents an attempt to perform both refresh and readwrite operations concurrently on identical said memory cells.
19. The SOC device of claim 18, wherein the collision avoidance mechanism compares the refresh addresses with the readwrite addresses to determine whether the attempt is made to perform both the refresh and readwrite operations concurrently on the identical said memory cells.
20. The SOC device of claim 19, wherein at least one of the refresh addresses is updated to prevent the attempt to perform both the refresh and readwrite operations concurrently on the identical said memory cells.
21. The SOC device of claim 20, wherein the at least one of the refresh addresses is updated by being changed by at least one.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus comprising:
a multi-path integrated device, the multi-path integrated device having a first output and a second output, where the first output is configured to be coupled to a first output lead through a first bonding wire and where the second output is configured to be coupled to a second output lead through a second bonding wire, and where the second bonding wire has a first mutual inductance with the first bonding wire; and
a first compensation network coupled to the first output and a second compensation network coupled to the second output, the second compensation network configured to have a second mutual inductance with the first compensation network, the second mutual inductance configured to at least partially cancel effects of the first mutual inductance.
2. The apparatus of claim 1 wherein the first compensation network and the second compensation network comprise bonding wires having a relative coiling direction opposite the first bonding wire and the second bonding wire.
3. The apparatus of claim 1 wherein the first compensation network and the second compensation network comprise interleaved integrated passive inductors.
4. The apparatus of claim 1 wherein the first compensation network is coupled between the first bonding wire and the first output lead and wherein the second compensation network is coupled between the second bonding wire and the second output lead.
5. The apparatus of claim 4 wherein the first compensation network and the second compensation network comprise proximate conductors that provide negative mutual inductance compared to a mutual inductance between the first bonding wire and the second bonding wire.
6. The apparatus of claim 1 wherein the first compensation network is coupled between the multi-path integrated device and the first bonding wire and wherein the second compensation network is coupled between the multi-path integrated device and the second bonding wire.
7. The apparatus of claim 6 wherein the first compensation network and the second compensation network comprise integrated passive inductors.
8. The apparatus of claim 7 wherein the integrated passive inductors are interleaved to provide negative mutual inductance compared to a mutual inductance between the first bonding wire and the second bonding wire.
9. The apparatus of claim 1 wherein the multi-path integrated device comprises a first amplifier and a second amplifier, the first amplifier coupled to the first output and the second amplifier coupled to the second output.
10. The apparatus of claim 9 wherein the first amplifier is a main amplifier of a Doherty amplifier, and the second amplifier is a peaking amplifier of the Doherty amplifier.
11. The apparatus of claim 1 wherein the multi-path integrated device additionally comprises a first input and a second input, where the first input is configured to be coupled to a first input lead through a third bonding wire and where the second input is configured to be coupled to a second input lead through a fourth bonding wire, and where the third bonding wire has a third mutual inductance with the fourth bonding wire, and wherein the apparatus further comprises:
a third compensation network coupled to the first input and a fourth compensation network coupled to the second input, the fourth compensation network configured to have a fourth mutual inductance with the third compensation network, the fourth mutual inductance configured to at least partially cancel effects of the third mutual inductance.
12. A packaged integrated circuit device comprising:
one or more semiconductor die including a multi-path amplifier, the multi-path amplifier including a first output and a second output;
a package encasing the semiconductor die, the package including a first output lead and a second output lead, the first output lead coupled to the first output through a first bonding wire and the second output lead coupled to the second output through a second bonding wire, where the second bonding wire has a first mutual inductance with the first bonding wire; and
a first compensation network coupled to the first output and a second compensation network coupled to the second output, the second compensation network configured to have a second mutual inductance with the first compensation network, the second mutual inductance configured to at least partially cancel effects of the first mutual inductance.
13. The packaged integrated circuit device of claim 12 wherein the first compensation network is coupled between the first bonding wire and the first output lead and wherein the second compensation network is coupled between the second bonding wire and the second output lead.
14. The packaged integrated circuit device of claim 12 wherein the first compensation network is coupled between the multi-path amplifier and the first bonding wire and wherein the second compensation network is coupled between the multi-path amplifier and the second bonding wire.
15. The packaged integrated circuit device of claim 14 wherein the first compensation network and the second compensation network comprise interleaved integrated passive inductors.
16. The packaged integrated circuit device of claim 12 wherein the multi-path amplifier additionally comprises a first input and a second input, and wherein the package further includes a first input lead and a second input lead, the first input lead coupled to the first input through a third bonding wire and the second input lead coupled to the second input through a fourth bonding wire, and where the third bonding wire has a third mutual inductance with the fourth bonding wire, and wherein the packaged integrated circuit device further comprises:
a third compensation network coupled to the first input and a fourth compensation network coupled to the second input, the fourth compensation network configured to have a fourth mutual inductance with the third compensation network, the fourth mutual inductance configured to at least partially cancel effects of the third mutual inductance.
17. A method comprising:
providing a semiconductor die including a multi-path device, the multi-path device including a first output and a second output;
coupling a first output lead to the first output through a first bonding wire;
coupling a second output lead to the second output through a second bonding wire, where the second bonding wire has a first mutual inductance with the first bonding wire;
coupling a first compensation network to the first output; and
coupling a second compensation network to the second output, the second compensation network configured to have a second mutual inductance with the first compensation network, the second mutual inductance configured to at least partially cancel effects of the first mutual inductance.
18. The method of claim 17 wherein the first compensation network is coupled between the first bonding wire and the first output lead and wherein the second compensation network is coupled between the second bonding wire and the second output lead.
19. The method of claim 17 wherein the first compensation network is coupled between the multi-path device and the first bonding wire and wherein the second compensation network is coupled between the multi-path device and the second bonding wire.
20. The method of claim 17 wherein the multi-path device additionally comprises a first input and a second input, and further comprising:
coupling the first input to a first input lead through a third bonding wire;
coupling the second input to a second input lead through a fourth bonding wire, where the third bonding wire has a third mutual inductance with the fourth bonding wire;
coupling a third compensation network to the first input; and
coupling a fourth compensation network to the second input, the fourth compensation network configured to have a fourth mutual inductance with the third compensation network, the fourth mutual inductance configured to at least partially cancel effects of the third mutual inductance.