1460927631-35e39e8d-9a63-4951-a9ff-bbe70ca09682

1. A process for deploying a medical device including a shape memory alloy element having a martensite deformation temperature (Md) that is greater than a body temperature of a mammalian body, wherein the shape memory alloy element exhibits a restrained shape and a deployed shape for use in the mammalian body, the process comprising:
heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof;
deforming the shape memory alloy element into the restrained shape without generating stress-induced martensite;
maintaining the shape memory alloy element in the restrained shape; and
self-expanding the shape memory alloy element from the restrained shape to the deployed shape within the mammalian body.
2. The process for deforming a medical device of claim 1, wherein the martensite deformation temperature of the shape memory alloy element is about 50\xb0 C. or more than an austenite finish temperature (Af) of the shape memory alloy element.
3. The process of claim 1, wherein maintaining the shape memory alloy element in the restrained shape comprises positioning the medical device including the shape memory alloy element at least partially inside a hollow delivery system to hold the shape memory alloy element in the restrained shape.
4. The process of claim 3, further comprising cooling the medical device positioned at least partially inside the hollow delivery system to room temperature prior to self-expanding the shape memory alloy element.
5. The process of claim 3, wherein the hollow delivery system comprises a catheter.
6. The process of claim 1, wherein the shape memory alloy element is in an austenitic state at room temperature of about 22\xb0 C.
7. The process of claim 1, wherein the shape memory alloy element comprises nitinol.
8. The process of claim 1, wherein the medical device comprises a stent.
9. The process for deforming a medical device of claim 1, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof is performed by a light source.
10. The process for deforming a medical device of claim 1, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element with a heated fluid.
11. The process for deforming a medical device of claim 1, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element by ultrasonic vibration.
12. The process for deforming a medical device of claim 1, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element with a current source connected to the shape memory alloy element.
13. The process for deforming a medical device of claim 1, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element by rolling the shape memory alloy element on a warm plate.
14. A process for deploying a medical device including a shape memory alloy element having a martensite deformation temperature (Md) that is greater than a body temperature of a mammalian body, wherein the shape memory alloy element exhibits a restrained shape and a deployed shape for use in the mammalian body, the process comprising:
heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof;
while the shape memory alloy element is at or above the martensite deformation temperature, deforming the shape memory alloy element into the restrained shape without generating stress-induced martensite;
maintaining the shape memory alloy element in the restrained shape; and
self-expanding the shape memory alloy element from the restrained shape to the deployed shape within the mammalian body.
15. The process for deforming a medical device of claim 14, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof is performed by a light source.
16. The process for deforming a medical device of claim 14, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element with a heated fluid.
17. The process for deforming a medical device of claim 14, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element by ultrasonic vibration.
18. The process for deforming a medical device of claim 14, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element with a current source connected to the shape memory alloy element.
19. The process for deforming a medical device of claim 14, wherein heating the shape memory alloy element to a temperature at or above the martensite deformation temperature thereof comprises heating the shape memory alloy element by rolling the shape memory alloy element on a warm plate.
20. The process of claim 14, wherein the medical device comprises a stent.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A thin film transistor (TFT), a source of the TFT comprising a first source portion, a drain of the TFT comprising a first drain portion, wherein the first source portion and the first drain portion are disposed in the same layer as an active layer of the TFT and at two opposite sides of the active layer, and the first source portion and the first drain portion are in direct contact with the active layer respectively.
2. The TFT according to claim 1, wherein the first source portion and the first drain portion are made of a material obtained from subjecting the same material as the active layer to a conductivity treatment.
3. The TFT according to claim 1, wherein the active layer is made of a semiconductor material.
4. The TFT according to claim 1, wherein the TFT further comprises an etch stop layer disposed on the active layer, the first source portion as well as the first drain portion; the source further comprises a second source portion disposed on the etch stop layer; the drain further comprises the second drain portion disposed on the etch stop layer; wherein the second source portion is connected to the first source portion, and the second drain portion is connected to the first drain portion.
5. The TFT according to claim 4, wherein two first via holes penetrating through the etch stop layer and respectively above the first source portion and the first drain portion are disposed in the etch stop layer; the second source portion is connected to the first source portion through one first via hole above the first source portion, and the second drain portion is connected to the first drain portion through the other first via hole above the first drain portion.
6. The TFT according to claim 1, wherein the TFT further comprises a gate disposed above or below the active layer.
7. A TFT array substrate, comprising a plurality of pixel units, wherein each of the pixel units comprises a switch TFT, and the switch TFT is the TFT according to claim 1.
8. The TFT array substrate according to claim 7, wherein the TFT array substrate is an active matrix organic light emitting display (AMOLED) array substrate, each of the pixel units of the TFT array substrate further comprises a drive TFT, and wherein the drive TFT comprises:
a thin film transistor (TFT), wherein a source of the TFT comprises a first source portion, a drain of the TFT comprising a first drain portion, wherein the first source portion and the first drain portion are disposed in the same layer as an active layer of the TFT and at two opposite sides of the active layer, and the first source portion and the first drain portion are in direct contact with the active layer respectively.
9. The TFT array substrate according to claim 8, wherein the AMOLED array substrate further comprises a gate, a gate insulation layer, an etch stop layer and a store capacitance lower electrode, wherein a second via hole penetrating through both the etch stop layer and the gate insulation layer is disposed in the etch stop layer, the store capacitance lower electrode is connected to the gate of the drive TFT through the second via hole, and the store capacitance lower electrode is disposed in the same layer as the gate of the switch TFT.
10. The TFT array substrate according to claim 9, wherein a connection metal layer in the same layer as the second source portion and the second drain portion of the switch TFT is disposed in the second via hole, the gate of the drive TFT is connected to the store capacitance lower electrode through the connection metal layer.
11. The TFT array substrate according to claim 10, wherein the AMOLED array substrate further comprises a pixel electrode, the pixel electrode is connected to the second drain portion of the switch TFT.
12. A display device, comprising the TFT array substrate according to claim 7.
13. A method of manufacturing a TFT array substrate, comprising:
forming a first source portion pattern of a source, a first drain portion pattern of a drain, and an active layer pattern on a base substrate by patterning process, wherein the first source portion and the first drain portion are respectively disposed at two opposite sides of an active layer and in direct contact with the active layer; and
performing a conductivity treatment on the first source portion and the first drain portion.
14. The method according to claim 13, wherein the conductivity treatment comprises hydrogen plasma treatment.
15. The method according to claim 13, wherein the method further comprises the following step before performing a conductivity treatment:
forming an etch stop layer pattern on the base substrate with the active layer formed thereon by patterning process, wherein two first via holes penetrating through the etch stop layer and respectively above the first source portion and the first drain portion are formed in the etch stop layer.
16. The method according to claim 15, further comprising:
forming a second source portion pattern of the source and a second drain portion pattern of the drain on the base substrate with the etch stop layer formed thereon by patterning process; the second source portion is connected to the first source portion through one first via hole above the first source portion, and the second drain portion is connected to the first drain portion through the other first via hole above the first drain portion.
17. The method according to claim 16, further comprising:
forming a gate and a passivation layer on the base substrate with the second source portion and the second drain portion formed thereon by patterning process.
18. The method according to claim 13, wherein before the step of forming the first source portion pattern of the source, the first drain portion pattern of the drain and the active layer pattern, the method further comprises:
forming a gate pattern and a gate insulation layer on the base substrate by patterning process.
19. The method according to claim 18, wherein the TFT array substrate is an active matrix organic light emitting display (AMOLED) array substrate, the method further comprises the following step while simultaneously forming the gate pattern on the base substrate:
forming a store capacitance lower electrode pattern in the same layer as the gate.
20. The method according to claim 19, wherein the step of forming the etch stop layer pattern on the base substrate with the active layer formed thereon by patterning process further comprises:
forming a second via hole which penetrates through both the etch stop layer and the gate insulation layer in the etch stop layer; wherein the store capacitance lower electrode is connected to the gate of the drive TFT by the second via hole.