1. A method comprising:
detecting a cache miss for a requested cache line in a cache sectored into superlines, each superline including multiple cache lines;
generating a request vector in response to detecting the cache miss, the request vector including a field for each cache line of the superline, the generating including placing a demand request in the field for the cache line that caused the cache miss;
modifying the request vector with prefetch hint information for one or more of the other cache lines allocated in the superline; and
sending the request vector to a higher level memory to cause the higher level memory to satisfy the demand request, wherein the higher level memory selectively either performs prefetches for other cache lines of the superline based on the prefetch hint information or drops the prefetch hint information.
2. The method of claim 1, wherein detecting the cache miss is performed by a cache controller, which generates the request vector and sends the request vector to a memory controller.
3. The method of claim 1, wherein modifying the request vector with prefetch hint information further comprises:
identifying a state of each cache line allocated in the superline; and
marking the field of one or more cache lines with a prefetch request.
4. The method of claim 3, wherein the higher level memory selectively drops the prefetch request based on workload at the higher level memory.
5. The method of claim 3, wherein marking the field of one or more cache lines with the prefetch request comprises:
selectively not marking the field of an invalid cache line with a prefetch request.
6. The method of claim 5, wherein selectively not marking the field of the invalid cache line with a prefetch request comprises:
determining how many cache lines in the superline are valid; and
only marking the field of the invalid cache line with a prefetch request if more than a threshold number of cache lines in the superline are valid.
7. The method of claim 3, further comprising:
allocating space in a prefetch buffer for a cache line whose field is marked with a prefetch request only if the higher level memory performs a prefetch for the cache line and returns the data for the cache line.
8. The method of claim 1, further comprising:
receiving prefetch data for a prefetched cache line from the higher level memory; and
returning credit metadata to the higher level memory in response to receiving the prefetch data.
9. The method of claim 8, wherein returning the credit metadata further comprises:
searching the cache for a superline associated with the prefetch cache line; and
indicating to the higher level memory when the search returns a superline miss.
10. An apparatus comprising:
a first memory in a memory hierarchy, the first memory including a first controller having a prefetch servicing engine; and
a second memory in the memory hierarchy, sectored into superlines that each include multiple cache lines, where the second memory is closer to a processor device that executes operations based on data stored in the memory hierarchy, the second memory including a second controller having a prefetch request engine;
wherein the second controller is to detect a cache miss for a requested cache line;
generate a request vector with the prefetch request engine in response to detecting the cache miss, the request vector including a field for each cache line of the superline, the generating including providing a demand request in the field for the cache line that caused the cache miss;
modify the request vector with prefetch hint information for one or more of the other cache lines allocated in the superline; and send the request vector to the prefetch servicing engine of the second controller to cause the second controller to satisfy the demand request, wherein the second controller selectively either performs prefetches for other cache lines of the superline based on the prefetch hint information or drops the prefetch hint information.
11. The apparatus of claim 10, wherein the first memory is a main system memory and the first controller is a memory controller, and the second memory is a cache memory and the second controller is a cache controller.
12. The apparatus of claim 10, wherein the second controller is to modify the request vector with prefetch hint information including
identifying a state of each cache line allocated in the superline; and
marking the field of one or more cache lines with a prefetch request.
13. The apparatus of claim 12, wherein the first controller is to selectively drop the prefetch request based on workload at the first memory.
14. The apparatus of claim 12, wherein the second controller is to marking the field of one or more cache lines with the prefetch request including
selectively not marking the field of an invalid cache line with a prefetch request.
15. The apparatus of claim 10, further comprising the second controller to receive prefetch data for a prefetched cache line from the first controller, and return credit metadata to the first controller in response to receiving the prefetch data.
16. An electronic device comprising:
a memory subsystem organized as a memory hierarchy, including
a first memory in a memory hierarchy, the first memory including a first controller having a prefetch servicing engine; and
a second memory in the memory hierarchy, sectored into superlines that each include multiple cache lines, where the second memory is closer to a processor device that executes operations based on data stored in the memory hierarchy, the second memory including a second controller having a prefetch request engine;
wherein the second controller is to detect a cache miss for a requested cache line; generate a request vector with the prefetch request engine in response to detecting the cache miss, the request vector including a field for each cache line of the superline, the generating including providing a demand request in the field for the cache line that caused the cache miss; modify the request vector with prefetch hint information for one or more of the other cache lines allocated in the superline; and send the request vector to the prefetch servicing engine of the second controller to cause the second controller to satisfy the demand request, wherein the second controller selectively either performs prefetches for other cache lines of the superline based on the prefetch hint information or drops the prefetch hint information; and
a touchscreen display coupled to generate a display based on data accessed from the memory subsystem.
17. The electronic device of claim 16, wherein the second controller is to modify the request vector with prefetch hint information including
identifying a state of each cache line allocated in the superline; and
marking the field of one or more cache lines with a prefetch request.
18. The electronic device of claim 17, wherein the first controller is to selectively drop the prefetch request based on workload at the first memory.
19. The electronic device of claim 17, wherein the second controller is to marking the field of one or more cache lines with the prefetch request including
selectively not marking the field of an invalid cache line with a prefetch request.
20. The electronic device of claim 16, further comprising the second controller to receive prefetch data for a prefetched cache line from the first controller, and return credit metadata to the first controller in response to receiving the prefetch data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A drive method of a light-emitting display panel comprising a plurality of drive lines and a plurality of scan lines intersecting one another, and a plurality of capacitive light-emitting elements connected between the respective drive lines and the respective scan lines at the positions at which the drive lines intersect the scan lines, comprising the step of:
changing, when the capacitive light-emitting elements constituting the light-emitting display panel start to emit light, a charge voltage, that is, a charge peak current for precharging the parasitic capacitances of the light-emitting elements according to the controlled state of the light emission luminance of the light-emitting elements.
2. The drive method of a light-emitting display panel according to claim 1, wherein the charge voltage for precharging the parasitic capacitances of the light-emitting elements is changed from a low voltage to a high voltage as the light emission luminance of the light-emitting elements is controlled from low luminance to high luminance.
3. The drive method of a light-emitting display panel according to claim 1, wherein a reverse bias voltage for applying a reverse bias to the light-emitting elements in a non-scan state is used as the charge voltage for precharging the parasitic capacitances of the light-emitting elements.
4. The drive method of a light-emitting display panel according to claim 2, wherein a reverse bias voltage for applying a reverse bias to the light-emitting elements in a non-scan state is used as the charge voltage for precharging the parasitic capacitances of the light-emitting elements.
5. The drive method of a light-emitting display panel according to claim 3, wherein precharge means for precharging the parasitic capacitances of the light-emitting elements executes a reset operation for resetting the voltages of both the terminals of the respective light-emitting elements to the same potential once when a scan is switched to the next scan and executes a charge operation subsequent to the reset operation for charging a charge current resulting from the reverse bias voltage to the parasitic capacitances of the light-emitting elements that are to be lit next via the parasitic capacitances of the other light-emitting elements commonly connected to the above drive lines together with the light-emitting elements.
6. The drive method of a light-emitting display panel according to claim 1, wherein the light emission luminance of the light-emitting elements is controlled by the lighting time of the light-emitting elements that are lit and displayed in one scan period.
7. The drive method of a light-emitting display panel according to claim 3 or 4, wherein the reverse bias voltage for precharging the parasitic capacitances of the light-emitting elements is created based on the voltage output from a drive voltage source for driving constant current circuits for applying constant currents to the respective drive lines.
8. The drive method of a light-emitting display panel according to claim 7, wherein the reverse bias voltage for precharging the parasitic capacitances of the light-emitting elements is obtained by dividing the voltage output from the drive voltage source based on a degree of control of the light emission luminance of the light-emitting elements.
9. The drive method of a light-emitting display panel according to claim 7, wherein a voltage increasing type DC-DC converter is used as the drive voltage source.
10. The drive method of a light-emitting display panel according to claim 8, wherein a voltage increasing type DC-DC converter is used as the drive voltage source.
11. An organic EL display device, wherein the light-emitting elements comprise organic EL elements driven for light emission by the drive method according to any one of claims 1 to 6.
12. An organic EL display device, wherein the light-emitting elements comprise organic EL elements driven for light emission by the drive method according to claim 7.
13. An organic EL display device, wherein the light-emitting elements comprise organic EL elements driven for light emission by the drive method according to claim 8.
14. An organic EL display device, wherein the light-emitting elements comprise organic EL elements driven for light emission by the drive method according to claim 9.
15. An organic EL display device, wherein the light-emitting elements comprise organic EL elements driven for light emission by the drive method according to claim 10.