1. A method of manufacturing a semiconductor device comprising: semiconductor elements; element isolation trenches each for isolation between the semiconductor elements formed in a MISFET formation region arranged in a first well; capacitor formation trenches formed in capacitor formation regions arranged in a second well separated from the first well; and capacitor electrodes each formed inside the capacitor formation trenches via a dielectric film,
the method comprising steps of:
(a) forming the capacitor formation trenches in capacitor formation regions arranged in said second well separated from said first well by a step of forming the element isolation trenches in a semiconductor substrate;
(b) embedding insulating films in the element isolation trenches formed in the MISFET formation region arranged in the first well and in the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the element isolation trenches; and
(d) forming gate electrodes in the MISFET formation region by a step of forming capacitor electrodes in the capacitor formation regions.
2. A method of manufacturing a semiconductor device having MISFETs and capacitors, comprising the steps of:
(a) forming element isolation trenches each for isolation between the MISFETs in a semiconductor substrate, and forming capacitor formation trenches in the semiconductor substrate;
(b) embedding insulating films in the element isolation trenches and the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the isolation element trenches;
(d) forming a first well in the semiconductor substrate, the first well surrounding a MISFET of said MISFETs;
(e) forming a second well in the semiconductor substrate, the second well surrounding the capacitor formation trenches, the second well being separated from the first well; and
(f) forming a gate insulating film of the MISFETs over the first well, and forming a capacitor dielectric film over the capacitor formation trenches.
3. A method of manufacturing a semiconductor device having MISFETs and capacitors, comprising the steps of:
(a) forming element isolation trenches each for isolation between the MISFETs in a semiconductor substrate, and forming capacitor formation trenches in the semiconductor substrate;
(b) embedding insulating films in the element isolation trenches and the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the isolation element trenches;
(d) forming a first well in the semiconductor substrate, the first well surrounding a MISFET of said MISFETs;
(e) forming a second well in the semiconductor substrate, the second well surrounding the capacitor formation trenches, the second well being separated from the first well;
(f) forming a gate insulating film of the MISFETs over the first well, and forming a capacitor dielectric film over the capacitor formation trenches; and
(g) forming gate electrodes of the MISFETs over the gate insulating film, and forming capacitor electrodes over the capacitor dielectric film.
4. A method of manufacturing a semiconductor device having memory cells, MISFETs and capacitors, comprising the steps of:
(a) forming element isolation trenches each for isolation between the MISFETs and between the memory cells in a semiconductor substrate, and forming capacitor formation trenches in the semiconductor substrate;
(b) embedding insulating films in the element isolation trenches and the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the isolation element trenches;
(d) forming a first well in the semiconductor substrate, the first well surrounding a MISFET of said MISFETs;
(e) forming a second well in the semiconductor substrate, the second well surrounding the capacitor formation trenches, the second well being separated from the first well;
(f) forming a third well in the semiconductor substrate, the third well surrounding the memory cells, the third well being separated from the first and second wells;
(g) forming a gate insulating film of the MISFETs over the first well, and forming a capacitor dielectric film over the capacitor formation trenches;
(h) forming a first memory gate insulating film over the third well; and
(i) forming an electric charge storage layer over the first memory gate insulating film, forming gate electrodes over the gate insulating film, and forming capacitor electrodes over the capacitor dielectric film.
5. A method of manufacturing a semiconductor device having memory cells, MISFETs and capacitors, comprising the steps of:
(a) forming element isolation trenches each for isolation between the MISFETs and between the memory cells in a semiconductor substrate, and forming capacitor formation trenches in the semiconductor substrate;
(b) embedding insulating films in the element isolation trenches and the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the isolation element trenches;
(d) forming a first well in the semiconductor substrate, the first well surrounding a MISFET of said MISFETs;
(e) forming a second well in the semiconductor substrate, the second well surrounding the capacitor formation trenches, the second well being separated from the first well;
(f) forming a third well in the semiconductor substrate, the third well surrounding the memory cells, the third well being separated from the first and second wells;
(g) forming a gate insulating film of the MISFETs over the first well, and forming a capacitor dielectric film over the capacitor formation trenches;
(h) forming a first memory gate insulating film over the third well;
(i) forming an electric charge storage layer over the first memory gate insulating film;
(j) forming a second memory gate insulating film over the electric charge storage layer; and
(k) forming memory gate electrodes over the second memory gate insulating film, forming gate electrodes over the gate insulating film, and forming capacitor electrodes over the capacitor dielectric film.
6. A method of manufacturing a semiconductor device having memory cells, MISFETs and capacitors, comprising the steps of:
(a) forming element isolation trenches each for isolation between the MISFETs and between the memory cells in a semiconductor substrate, and forming capacitor formation trenches in the semiconductor substrate;
(b) embedding insulating films in the element isolation trenches and the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the isolation element trenches;
(d) forming a first well in the semiconductor substrate, the first well surrounding a MISFET of said MISFETs;
(e) forming a second well in the semiconductor substrate, the second well surrounding the capacitor formation trenches, the second well being separated from the first well;
(f) forming a third well in the semiconductor substrate, the third well surrounding the memory cells, the third well being separated from the first and second wells;
(g) forming a gate insulating film of the MISFETs over the first well;
(h) forming a first memory gate insulating film over the third well;
(i) forming an electric charge storage layer over the first memory gate insulating film;
(j) forming a second memory gate insulating film over the electric charge storage layer, and forming a capacitor dielectric film over the capacitor formation trenches; and
(k) forming memory gate electrodes over the second memory gate insulating film, forming gate electrodes of the MISFETs over the gate insulating film, and forming capacitor electrodes over the capacitor dielectric film.
7. A method of manufacturing a semiconductor device having memory cells and capacitors, comprising the steps of:
(a) forming element isolation trenches each for isolation between the memory cells in the semiconductor substrate, and forming capacitor formation trenches in the semiconductor substrate;
(b) embedding insulating films in the element isolation trenches and the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the isolation element trenches;
(d) forming a second well in the semiconductor substrate, the second well surrounding the capacitor formation trenches;
(e) forming a third well in the semiconductor substrate, the third well surrounding the memory cells, the third well being separated from the second well;
(f) forming a first memory gate insulating film over the third well;
(g) forming an electric charge storage layer over the first memory gate insulating film; and
(h) forming a second memory gate insulating film over the electric charge storage layer, and a capacitor dielectric film in the capacitor formation trenches.
8. A method of manufacturing a semiconductor device having memory cells and capacitors, comprising the steps of:
(a) forming element isolation trenches each for isolation between the memory cells in a semiconductor substrate, and forming capacitor formation trenches in the semiconductor substrate;
(b) embedding insulating films in the element isolation trenches and the capacitor formation trenches;
(c) removing the insulating film embedded in the capacitor formation trenches while leaving the insulating film embedded in the isolation element trenches;
(d) forming a second well in the semiconductor substrate, the second well surrounding the capacitor formation trenches;
(e) forming a third well in the semiconductor substrate, the third well surrounding the memory cells, the third well being separated from the second well;
(f) forming a first memory gate insulating film over the third well;
(g) forming an electric charge storage layer over the first memory gate insulating film;
(h) forming a second memory gate insulating film over the electric charge storage layer, and forming a capacitor dielectric film in the capacitor formation trenches; and
(i) forming memory gate electrodes over the second memory gate insulating film, and forming capacitor electrodes over the capacitor dielectric film.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a lattice.
10. The method of manufacturing a semiconductor device according to claim 1 wherein in the step (c), a part of the insulating film embedded in the element isolation trenches, and the insulating film embedded in the capacitor formation trenches, are removed, while leaving another part of the insulating film embedded in the element isolation trenches.
11. The method of manufacturing a semiconductor device according to claim 2, wherein the MISFETs include a first MISFET for high voltage and a second MISFET for low voltage, and
wherein the thickness of the gate insulating film of the first MISFET is larger than the thickness of the gate insulating film of the second MISFET.
12. The method of manufacturing a semiconductor device according to claim 5,
wherein the second memory gate insulating film and the capacitor dielectric film include a multilayer film comprised of a silicon oxide film and a silicon nitride film.
13. The method of manufacturing a semiconductor device according to claim 5,
wherein the electric charge storage layer includes a silicon nitride film or a Si nano-dot.
14. The method of manufacturing a semiconductor device according to claim 5,
wherein the electric charge storage layer includes a polysilicon film.
15. The method of manufacturing a semiconductor device according to claim 5,
wherein the memory gate electrodes include a polysilicon film.
16. The method of manufacturing a semiconductor device according to claim 1,
wherein the capacitor dielectric film and each of the capacitor electrodes are formed over a plurality of the capacitor formation trenches.
17. The method of manufacturing a semiconductor device according to claim 16,
wherein the plurality of the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
18. The method of manufacturing a semiconductor device according to claim 5, further comprising the steps of:
forming a charge pump circuit of a plurality of the MISFETs and a plurality of the capacitors; and
electrically connecting the charge pump circuit to the memory gate electrodes.
19. The method of manufacturing a semiconductor device according to claim 6, further comprising the steps of:
forming a charge pump circuit of a plurality of the MISFETs and a plurality of the capacitors; and
electrically connecting the charge pump circuit to the memory gate electrodes.
20. The method of manufacturing a semiconductor device according to claim 1, wherein said element isolation trenches are formed at least in part in an element isolation region separate from said capacitor formation regions.
21. The method of manufacturing a semiconductor device according to claim 11, wherein said capacitor dielectric film and the gate insulating film of the first MISFET are formed in a same step.
22. The method of manufacturing a semiconductor device according to claim 11, wherein said capacitor dielectric film and the gate insulating film of the second MISFET are formed in a same step.
23. The method of manufacturing a semiconductor device according to claim 3, wherein said gate electrodes and said capacitor electrodes are formed in a same step.
24. The method of manufacturing a semiconductor device according to claim 5, wherein said second memory gate insulating film and said capacitor dielectric film are formed in a same step.
25. The method of manufacturing a semiconductor device according to claim 8, wherein steps (d) and (e) are the same step.
26. The method of manufacturing a semiconductor device according to claim 8, wherein steps (d) and (e) are different steps.
27. The method of manufacturing a semiconductor device according to claim 7, wherein steps (d) and (e) are the same step.
28. The method of manufacturing a semiconductor device according to claim 7, wherein steps (d) and (e) are different steps.
29. The method of manufacturing a semiconductor device according to claim 6, wherein steps (d) and (e) are the same step.
30. The method of manufacturing a semiconductor device according to claim 6, wherein steps (d) and (e) are different steps.
31. The method of manufacturing a semiconductor device according to claim 5, wherein steps (d) and (e) are the same step.
32. The method of manufacturing a semiconductor device according to claim 5, wherein steps (d) and (e) are different steps.
33. The method of manufacturing a semiconductor device according to claim 4, wherein steps (d) and (e) are the same step.
34. The method of manufacturing a semiconductor device according to claim 4, wherein steps (d) and (e) are different steps.
35. The method of manufacturing a semiconductor device according to claim 3, wherein steps (d) and (e) are the same step.
36. The method of manufacturing a semiconductor device according to claim 3, wherein steps (d) and (e) are different steps.
37. The method of manufacturing a semiconductor device according to claim 2, wherein steps (d) and (e) are the same step.
38. The method of manufacturing a semiconductor device according to claim 2, wherein steps (d) and (e) are different steps.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory structure, comprising:
a first memory cell having a first plurality of non-volatile Semiconductor-Oxide-Nitride-Oxide-Semiconductor type (SONOS-type) devices coupled with a first Six Transistor (6-T) Static Random Access Memory (SRAM) cell;
a second memory cell having a second plurality of non-volatile SONOS-type devices coupled with a second 6-T SRAM cell, wherein the first plurality of non-volatile SONOS-type devices are interdigitated with the second plurality of non-volatile SONOS-type devices;
a store gate line, a non-volatile gate line, and a recall gate line, wherein the store gate line, the non-volatile gate line, and the recall gate line overlap diffusion areas of both the first and second pluralities of non-volatile SONOS-type devices; and
wherein each of the first and the second pluralities of non-volatile SONOS-type devices comprises an interconnect and a set of dummy interconnects.
2. The memory structure of claim 1, wherein the set of dummy interconnects is provided for increasing an electrical symmetry of the first and second memory cells by reducing a capacitance difference between the first and second memory cells.
3. The memory structure of claim 1, wherein the SONOS-type devices are 65 nanometer node devices.
4. The memory structure of claim 1, wherein the combination of the first and second memory cells has a total area, and wherein the total area of the first and second memory cells combined is approximately 2.5 by approximately 1.4 square microns.
5. The memory structure of claim 1, wherein alternating ones of the first plurality of non-volatile SONOS-type devices are interdigitated with corresponding alternating ones of the second plurality of non-volatile SONOS-type devices.
6. A method for fabricating a memory structure, comprising:
forming a first memory cell having a first plurality of non-volatile Semiconductor-Oxide-Nitride-Oxide-Semiconductor type (SONOS-type) devices coupled with a first Six Transistor (6-T) Static Random Access Memory (SRAM) cell;
forming a second memory cell having a second plurality of non-volatile SONOS-type devices coupled with a second 6-T SRAM cell, wherein the first plurality of non-volatile SONOS-type devices are interdigitated with the second plurality of non-volatile SONOS-type devices;
forming a store gate line, a non-volatile gate line, and a recall gate line, wherein each of the store gate line, the non-volatile gate line, and the recall gate line overlaps diffusion areas of both the first and second pluralities of non-volatile SONOS-type devices; and
forming a plurality of interconnects and a plurality of dummy interconnects, wherein each of the first and second pluralities of non-volatile SONOS-type devices is coupled with one of the plurality of interconnects and one of the plurality of dummy interconnects.
7. The method of claim 6, wherein forming the plurality of dummy interconnects comprises increasing an electrical symmetry of the first and second memory cells by reducing a capacitance difference between the first and second memory cells.
8. The method of claim 6, wherein forming the SONOS-type devices comprises forming 65 nanometer node devices.
9. The method of claim 6, wherein forming the first and second memory cells comprises forming the first and second memory cells to have a combined total area of approximately 2.5 by approximately 1.4 square microns.
10. The method of claim 6, wherein alternating ones of the first plurality of non-volatile SONOS-type devices are interdigitated with corresponding alternating ones of the second plurality of non-volatile SONOS-type devices.