1. A semiconductor device comprising:
a semiconductor chip, a function element being formed on a side corresponding to a front surface of the semiconductor chip;
a front side resin layer formed on the front surface of the semiconductor chip;
a back side resin layer formed on a back surface of the semiconductor chip, the back side resin layer being formed to be thinner than the front side resin layer,
wherein a groove is formed on the back side resin layer, and a plurality of external terminals are formed on the front side resin layer,
the groove includes engraved indicating information regarding the semiconductor device,
the back side resin layer has a higher thermal expansion coefficient than that of the front side resin layer, and
the back side resin layer has a smaller elasticity modulus than that of the front side resin layer, wherein the elasticity modulus is Young’s modulus.
2. The semiconductor device according to claim 1, wherein the semiconductor chip has a thickness of 300 to 400 \u03bcm.
3. The semiconductor device according to claim 1, wherein the front side resin layer has a thickness of 40 to 100 \u03bcm.
4. The semiconductor device according to claim 1, wherein the plurality of external terminals are arranged in a lattice pattern.
5. The semiconductor device according to claim 1, wherein each external terminal is formed in a ball shape.
6. The semiconductor device according to claim 1, wherein the back side resin layer has a thickness of 10 to 20 \u03bcm.
7. The semiconductor device according to claim 1, wherein the back side resin layer includes an epoxy resin.
8. The semiconductor device according to claim 1, wherein the back side resin layer includes a filler.
9. The semiconductor device according to claim 8, wherein a content of the filler in the back side resin layer is in a range not less than 5 weight percent and not more than 10 weight percent.
10. The semiconductor device according to claim 8, wherein the filler includes silica particles.
11. The semiconductor device according to claim 10, wherein a particle size of the silica particle is not more than 10 \u03bcm at a maximum.
12. The semiconductor device according to claim 1, wherein the groove does not reach to the semiconductor chip.
13. A semiconductor device comprising:
a semiconductor chip, a function element being formed on a side corresponding to a front surface of the semiconductor chip;
a front side resin layer formed on the front surface of the semiconductor chip;
a back side resin layer formed on a back surface of the semiconductor chip, the back side resin layer being formed to be thinner than the front side resin layer,
wherein a groove which does not reach to the semiconductor chip is formed on the back side resin layer, and a plurality of external terminals are formed on the front side resin layer, the plurality of external terminals being arranged in a lattice pattern, each external terminal being formed in a ball shape,
the groove includes engraved indicating information regarding the semiconductor device,
the back side resin layer has a higher thermal expansion coefficient than that of the front side resin layer, and
the back side resin layer has a smaller elasticity modulus than that of the front side resin layer, wherein the elasticity modulus is Young’s modulus.
14. The semiconductor device according to claim 13, wherein the semiconductor chip has a thickness of 300 to 400 \u03bcm.
15. The semiconductor device according to claim 13, wherein the front side resin layer has a thickness of 40 to 100 \u03bcm.
16. The semiconductor device according to claim 13, wherein the back side resin layer has a thickness of 10 to 20 \u03bcm.
17. The semiconductor device according to claim 13, wherein the back side resin layer includes an epoxy resin.
18. The semiconductor device according to claim 13, wherein the back side resin layer includes a filler.
19. The semiconductor device according to claim 18, wherein a content of the filler in the back side resin layer is in a range not less than 5 weight percent and not more than 10 weight percent.
20. The semiconductor device according to claim 18, wherein the filler includes silica particles.
21. The semiconductor device according to claim 20, wherein a particle size of the silica particle is not more than 10 \u03bcm at a maximum.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A controller employable with a power converter, comprising:
a peak detector, coupled to a circuit element of said power converter, configured to produce a signal corresponding to a peak current through said circuit element; and
an adjustable reference circuit responsive to a difference between said signal and a reference signal corresponding to a desired peak current to produce a corrected signal corresponding to said peak current.
2. The controller as recited in claim 1 wherein said circuit element is a power switch and said controller further comprises a comparator coupled to said peak detector and said adjustable reference circuit configured to disable conductivity of said power switch when said signal exceeds said corrected signal.
3. The controller as recited in claim 1 wherein said peak detector comprises a current sensor, an amplifier, a diode, and a capacitor.
4. The controller as recited in claim 3 wherein said current sensor comprises a resistor.
5. The controller as recited in claim 3 wherein said peak detector further comprises a resistor and a peak detector switch with conductivity switched at a frequency related to a switching frequency of said power converter to provide a discharge path for said capacitor.
6. The controller as recited in claim 1 wherein said adjustable reference circuit comprises an amplifier including a feedback capacitor.
7. The controller as recited in claim 1 wherein said adjustable reference circuit comprises digital logic and a digital-to-analog converter.
8. The controller as recited in claim 1 wherein said digital logic comprises an up-down counter.
9. The controller as recited in claim 1 wherein said corrected signal is limited by a first diode in an output path of said adjustable reference circuit and a second diode in a feedback path of said adjustable reference circuit.
10. The controller as recited in claim 1 wherein said corrected signal is limited by a first switch in an output path of said adjustable reference circuit and a second switch in a feedback path of said adjustable reference circuit.
11. A method employable with a power converter, comprising:
producing a signal corresponding to a peak current through a circuit element of said power converter;
producing a reference signal corresponding to a desired peak current associated with said circuit element; and
produce a corrected signal corresponding to said peak current responsive to a difference between said signal and said reference signal.
12. The method as recited in claim 11 wherein said circuit element is a power switch and further comprising disabling conductivity of said power switch when said signal exceeds said corrected signal.
13. The method as recited in claim 11 wherein said corrected signal is produced with digital logic and a digital-to-analog converter.
14. The method as recited in claim 11 further comprising limiting said corrected signal with a feedback circuit.
15. A power converter, comprising:
a circuit element coupled to an input of said power converter; and
a controller, coupled to said circuit element, comprising:
a peak detector configured to produce a signal corresponding to a peak current through said circuit element, and
an adjustable reference circuit responsive to a difference between said signal and a reference signal corresponding to a desired peak current to produce a corrected signal corresponding to said peak current.
16. The power converter as recited in claim 15 wherein said circuit element is a power switch and said controller further comprises a comparator coupled to said peak detector and said adjustable reference circuit configured to disable conductivity of said power switch when said signal exceeds said corrected signal.
17. The power converter as recited in claim 15 wherein said peak detector comprises a current sensor, an amplifier, a diode, and a capacitor.
18. The power converter as recited in claim 15 wherein said adjustable reference circuit comprises an amplifier including a feedback capacitor.
19. The power converter as recited in claim 15 wherein said adjustable reference circuit comprises digital logic and a digital-to-analog converter.
20. The power converter controller as recited in claim 15 wherein said corrected signal is limited by a first diode or switch in an output path of said adjustable reference circuit and a second diode or switch in a feedback path of said adjustable reference circuit.