What is claimed is:
1. A method for providing aggregate object identifiers, comprising:
obtaining a plurality of objects from a database, wherein each of the plurality of objects contains an unique identifier;
creating an aggregate object identifier by combining the unique identifiers of the plurality of objects into a single object; and
referencing one or more objects of interest in the database using the aggregate object identifier as a key.
2. The method of claim 1, further comprising referencing one or more baseline objects.
3. The method of claim 1, further comprising referencing one or more collection queue objects.
4. The method of claim 1, further comprising using a get method to reference the one or more objects of interest.
5. The method of claim 1, further comprising using a put method to reference the one or more objects of interest.
6. The method of claim 1, further comprising using an equals method and a hash code method to create the aggregate object identifier.
7. The method of claim 1, further comprising obtaining a repeatable name object, a device object, and a sub-component object from the database.
8. The method of claim 1, further comprising combining maps of the plurality of objects to create an aggregate object identifier map, wherein the aggregate object identifier is the key to the aggregate object identifier map.
9. An apparatus for providing aggregate object identifiers, comprising:
a retrieval module capable of obtaining a plurality of objects from a database, wherein each of the plurality of objects contains a unique identifier;
a creating module capable of creating an aggregate object identifier by combining the unique identifiers of the plurality of objects into a single object; and
a referencing module capable of referencing one or more objects of interest in the database using the aggregate object identifier as a key.
10. The apparatus of claim 9, wherein the referencing module references one or more baseline objects.
11. The apparatus of claim 9, wherein the referencing module references one or more collection queue objects.
12. The apparatus of claim 9, wherein the referencing module uses a get method to reference the one or more objects of interest.
13. The apparatus of claim 9, wherein the referencing module uses a put method to reference the one or more objects of interest.
14. The apparatus of claim 9, wherein the creating module uses an equals method and a hash code method to create the aggregate object identifier.
15. The apparatus of claim 9, wherein the retrieval module obtains a repeatable name object, a device object, and a sub-component object from the database.
16. The apparatus of claim 9, wherein the creating module combines maps of the plurality of objects to create an aggregate object identifier map, wherein the aggregate object identifier is the key to the aggregate object identifier map.
17. A computer readable medium providing instructions for providing aggregate object identifiers, the instructions comprising:
obtaining a plurality of objects from a database, wherein each of the plurality of objects contains an unique identifier;
creating an aggregate object identifier by combining the unique identifiers of the plurality of objects into a single object; and
referencing one or more objects of interest in the database using the aggregate object identifier as a key.
18. The computer readable medium of claim 17, further comprising instructions for referencing one or more baseline objects.
19. The computer readable medium of claim 17, further comprising instructions for referencing one or more collection queue objects.
20. The computer readable medium of claim 17, further comprising instructions for combining maps of the plurality of objects to create an aggregate object identifier map, wherein the aggregate object identifier is the key to the aggregate object identifier map.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A switching regulator comprising:
a power switch circuit including at least one power transistor switch which operates to convert an input voltage to an output voltage;
a PWM (Pulse Width Modulation) generation circuit for generating a duty signal in a normal operation mode according to a feedback signal relating to the output voltage;
a pulse skipping circuit for determining On-time in a pulse skipping mode according to a signal from a node with non-constant voltage level, the node being connected with the power transistor switch; and
a driver circuit for driving the at least one power transistor switch according to one of the outputs from the PWM generation circuit and the pulse skipping circuit.
2. The switching regulator of claim 1, wherein the pulse skipping circuit includes:
an average circuit for obtaining an average of the signal from the node and outputting a signal proportional to the average;
a sawtooth wave generator for generating a sawtooth wave signal according to the signal from the node, wherein the slope of the sawtooth wave signal relates to the input voltage; and
a comparator for comparing the output of the average circuit with the sawtooth wave signal to determine the On-time in the pulse skipping mode.
3. The switching regulator of claim 2, wherein the pulse skipping circuit further includes:
a minimum On-time generation circuit; and
a selection circuit for selecting a wider pulse width output from the outputs of the comparator and the minimum On-time generation circuit.
4. The switching regulator of claim 2, wherein the pulse skipping circuit further includes:
an oscillation circuit for generating a clock signal having a pulse width which is the minimum On-time; and
a flip-flop circuit generating an output signal whose rising edge is determined according to a rising edge of the clock signal, and whose falling edge is determined according to the later falling edge of the clock signal and the output of the comparator.
5. The switching regulator of claim 2, wherein the average circuit includes a low-pass filter for obtaining a DC (direct current) value of the signal from the node.
6. The switching regulator of claim 5, wherein the average circuit further includes a scale circuit for generating a signal proportional to the DC value.
7. The switching regulator of claim 2, wherein the sawtooth wave generator includes:
a voltage-to-current conversion circuit converting a voltage at the node to a current signal; and
a capacitor charged by the current signal, for generating the sawtooth wave signal.
8. A control circuit for controlling a switching regulator to convert an input voltage to an output voltage by operating at least one power transistor switch, the power transistor switch having a terminal coupled to a node with non-constant voltage level, the control circuit comprising:
a pin receiving a signal from the node with non-constant voltage level;
a PWM generation circuit for generating a duty signal in a normal operation mode according to a feedback signal relating to the output voltage;
a pulse skipping circuit for determining On-time in a pulse skipping mode according to the signal from the node; and
a driver circuit for generating a driver signal according to one of the outputs from the PWM generation circuit and the pulse skipping circuit.
9. The control circuit of claim 8, wherein the pulse skipping circuit includes:
an average circuit for obtaining an average of the signal from the node and outputting a signal proportional to the average;
a sawtooth wave generator for generating a sawtooth wave signal according to the signal from the node, wherein the slope of the sawtooth wave signal relates to the input voltage; and
a comparator for comparing the output of the average circuit with the sawtooth wave signal to determine the On-time in the pulse skipping mode.
10. The control circuit of claim 9, wherein the pulse skipping circuit further includes:
a minimum On-time generation circuit; and
a selection circuit for selecting a wider pulse width output from the outputs of the comparator and the minimum On-time generation circuit.
11. The control circuit of claim 9, wherein the pulse skipping circuit further includes:
an oscillation circuit for generating a clock signal having a pulse width which is the minimum On-time; and
a flip-flop circuit for generating an output signal whose rising edge is determined according to a rising edge of the clock signal, and whose falling edge is determined according to the later falling edge of the clock signal and the output of the comparator.
12. The control circuit of claim 9, wherein the average circuit includes a low-pass filter for obtaining a DC value of the signal from the node.
13. The control circuit of claim 12, wherein the average circuit further includes a scale circuit for generating a signal proportional to the DC value.
14. The control circuit of claim 9, wherein the sawtooth wave generator includes:
a voltage-to-current conversion circuit converting a voltage at the node to a current signal; and
a capacitor charged by the current signal, for generating the sawtooth wave signal.
15. A method for determining On-time in a switching regulator which converts an input voltage to an output voltage by operating at least one power transistor switch, the power transistor switch having a terminal coupled to a node with a non-constant voltage level, the method comprising the steps of:
generating a signal relating to an average of a signal from the node;
generating a sawtooth wave signal according to the signal from the node, wherein the slope of the sawtooth wave signal relates to the input voltage; and
determining On-time in the pulse skipping mode by comparing the signal relating to the average of the signal from the node with the sawtooth wave signal.
16. The method of claim 15, wherein the step of generating the signal relating to the average of the signal from the node includes:
low-pass filtering the signal from on the node.
17. The method of claim 15, wherein the step of generating the signal relating to the average of the signal from the node further includes:
generating a signal proportional to the DC value of the signal from the node.
18. The method of claim 15, wherein the step of generating the sawtooth wave signal includes:
converting a voltage at the node to a current signal; and
charging a capacitor by the current signal, to generate the sawtooth wave signal.
19. The method of claim 15 further comprising:
determining a minimum On-time; and
determining On-time by selecting a longer one of the minimum On-time and the On-time in the pulse skipping mode determined by the comparing step.
20. The method of claim 15 further comprising:
generating a clock signal having a pulse width which is the minimum On-time; and
determining a start time of the On-time in the pulse skipping mode according to a rising edge of the clock signal, and an end time according to the later of a falling edge of the clock signal and the end time of the On-time in the pulse skipping mode determined in the comparing step.