1. A method of manufacturing a catalytic converter a catalyst whose outer peripheral surface is wrapped with a mat, and an outer cylindrical housing which includes at least a reduced-diameter portion to support therein the catalyst and the mat, the method comprising the steps of:
providing a pressing device, and thereby press-fitting the catalyst and the mat into the outer cylindrical housing along a longitudinal direction of the outer cylindrical housing;
a detecting step of detecting a longitudinal pressing force at a time when at least a portion of the catalyst is within an enlarged-diameter portion of the outer cylindrical housing while the pressing device is pressing the catalyst and the mat in the longitudinal direction into the outer cylindrical housing;
a determining step of determining a diameter reduction of the outer cylindrical housing, by which a clearance value between the outer cylindrical housing and the catalyst is set to a desired target value, as a function of the longitudinal pressing force detected by the detecting step; and
a swaging step of reducing a diameter of the outer cylindrical housing based on the diameter reduction calculated by the determining step.
2. The method as claimed in claim 1, wherein the outer cylindrical housing is swaged in the swaging step after the catalyst is press-fitted into the outer cylindrical housing.
3. The method as claimed in claim 2, wherein the press-fitting of the catalyst is carried out using a funnel-shaped enlarged diameter member, and wherein the detection of the pressing force by the detecting step is carried out by detecting a pressing force upon press-fitting the catalyst into the reduced-diameter portion.
4. The method as claimed in claim 3, wherein the enlarged diameter member comprises an inclined portion, and the reduced-diameter portion includes a cylindrical portion having a straight inner surface which continuously extends from the inclined portion, and wherein the detection of the pressing force by the detecting step is carried out at a position just before a rear end portion of the mat enters from the inclined portion into the cylindrical portion as viewed in a press-fitting direction of the catalyst.
5. The method as claimed in claim 4, wherein the cylindrical portion is formed to have a length such that at least an entire length of the catalyst is received therein.
6. The method as claimed in claim 4, wherein the press-fitting direction of the catalyst is the longitudinal direction.
7. The method as claimed in claim 2, wherein the detection of the pressing force by the detecting step is carried out by detecting a pressing force of the catalyst after the catalyst is press-fitted into the outer cylindrical housing.
8. The method as claimed in claim 2, further comprising a pre-swaging step for providing a reduced diameter portion on the outer cylindrical housing by a swaging process, in which swaging is performed with a smaller diameter reduction than the diameter reduction in the swaging step, and for providing an inclined stepped portion between this reduced diameter portion and a non-swaged portion, and wherein the detection of the pressing force by the detecting step is carried out at a position just before a rear end portion of the mat enters from the stepped portion into the reduced diameter portion as viewed in a press-fitting direction of the catalyst.
9. The method as claimed in claim 2, further comprising a press-fitting step for temporarily stopping a press-fitting operation after the catalyst is entirely press-fitted inside the outer cylindrical housing, and a re-press-fitting step for restarting the press-fitting operation temporarily stopped by the press-fitting step and re-press-fitting the catalyst, and wherein the detection of the pressing force by the detecting step is carried out in the re-press-fitting step.
10. The method as claimed in claim 2, wherein the calculation of the diameter reduction by the calculating step is carried out based on data which are previously set in accordance with kinds of mats, catalysts, and outer cylindrical housings.
11. The method as claimed in claim 2, wherein the calculation of the diameter reduction by the calculating step is carried out based on a peak value of the pressing force detected by the detecting step at a predetermined insertion position.
12. The method as claimed in claim 2, wherein a sheet made of polypropylene or polyethylene terephthalate is attached to an outer surface of the mat.
13. The method as claimed in claim 1, wherein the catalyst is press-fitted into the outer cylindrical housing after the outer cylindrical housing is swaged.
14. The method as claimed in claim 1, further comprising:
controlling a plurality of the catalytic converters for checking on acceptancerejection of each catalytic converter, by including in the determining step; and
pressing the catalyst in the swaged outer cylindrical housing to determine whether or not the catalyst is supported by a predetermined packing density.
15. The method as claimed in claim 14, wherein the determining step is carried out after the catalyst is press-fitted into the outer cylindrical housing.
16. The method as claimed in claim 14, wherein the determination step is carried out after the outer cylindrical housing is swaged and in the process of press-fitting the catalyst into the outer cylindrical housing.
17. The method as claimed in claim 14, wherein a sheet made of polypropylene or polyethylene terephthalate is attached to an outer surface of the mat.
18. The method as claimed in claim 1, wherein the longitudinal direction is substantially parallel to an axis of the outer cylindrical housing.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A manufacturing method of a vertical channel transistor array, comprising:
providing a semiconductor substrate;
forming a plurality of first trenches in the semiconductor substrate, wherein the first trenches are arranged in parallel and extended along a column direction;
forming a plurality of embedded bit lines at bottoms of the first trenches;
forming a plurality of bit line contacts, each of the bit line contacts being formed on a side surface of one of the embedded bit lines, wherein the embedded bit lines are electrically connected to the semiconductor substrate through the bit line contacts;
forming a plurality of second trenches in the semiconductor substrate, wherein the second trenches are arranged in parallel and extended along a row direction, and the semiconductor substrate is divided into a plurality of semiconductor pillars by the first trenches and the second trenches;
forming a gate dielectric layer on surfaces of the semiconductor pillars;
forming a plurality of embedded word lines at bottoms of the second trenches; and
forming a current leakage isolation structure in the semiconductor substrate to prevent current leakage between adjacent bit line contacts, wherein the current leakage isolation structure is disposed at terminals of the embedded bit lines.
2. The manufacturing method of the vertical channel transistor array as claimed in claim 1, wherein the current leakage isolation structure is a shallow trench isolation structure.
3. The manufacturing method of the vertical channel transistor array as claimed in claim 1, wherein the step of forming the current leakage isolation structure is before the step of forming the first trenches in the semiconductor substrate.
4. The manufacturing method of the vertical channel transistor array as claimed in claim 2, wherein the shallow trench isolation structure comprises a plurality of shallow trench isolation blocks.
5. The manufacturing method of the vertical channel transistor array as claimed in claim 1, wherein the current leakage isolation structure is a doped region.
6. The manufacturing method of the vertical channel transistor array as claimed in claim 5, wherein a method of forming the doped region comprises ion implantation.
7. The manufacturing method of the vertical channel transistor array as claimed in claim 1, wherein the step of forming the current leakage isolation structure is after the step of forming embedded word lines in the semiconductor substrate.
8. The manufacturing method of the vertical channel transistor array as claimed in claim 1, further comprising forming a current leakage isolation doped region in the semiconductor substrate located below the embedded bit lines to prevent the adjacent bit line contacts from generating current leakage at bottoms of the embedded bit lines.
9. The manufacturing method of the vertical channel transistor array as claimed in claim 1, further comprising forming an insulating layer between each of the embedded bit lines and the semiconductor substrate.
10. The manufacturing method of the vertical channel transistor array as claimed in claim 9, the step of forming the embedded bit lines at the bottoms of the first trenches and the step of forming each of the bit line contacts at the one side of one of the embedded bit lines comprising:
forming the insulating layer on the semiconductor substrate;
forming a trench filling material layer in the first trenches, a first distance existing between a surface of the trench filling material layer and top surfaces of the first trenches;
forming a first liner layer on a surface of the insulating layer exposed by the trench filling material layer;
removing a portion of the trench filling material layer, such that a second distance exists between the surface of the trench filling material layer and the top surfaces of the first trenches, wherein the second distance is greater than the first distance;
forming a second liner layer on a surface of the first liner and the surface of the insulating layer exposed by the trench filling material layer;
removing the second liner layer located at a first side of each of the first trenches;
removing the insulating layer exposed by the first liner layer;
removing the remaining second liner layer;
sequentially forming a first barrier layer and a first conductive layer in each of the first trenches, each of the first trenches being filled with the first conductive layer;
removing a portion of the first conductive layer and a portion of the first barrier layer, so as to form the embedded bit lines at the bottoms of the first trenches; and
forming the bit line contacts at the sides of the embedded bit lines by causing a reaction between the first barrier layers and the semiconductor substrate.
11. The manufacturing method of the vertical channel transistor array as claimed in claim 1, the step of forming the embedded word lines at the bottoms of the second trenches comprising:
sequentially forming a second barrier layer and a second conductive layer in each of the second trenches;
removing a portion of the second barrier layer and a portion of the second conductive layer, such that a surface of the second conductive layer and the second barrier layer are lower than a surface of the semiconductor substrate;
forming a mask layer on side walls of each of the second trenches; and
removing the remaining second barrier layer and the remaining second conductive layer with use of the mask layer as a mask, so as to form the embedded word lines.
12. The manufacturing method of the vertical channel transistor array as claimed in claim 1, wherein the step of forming the current leakage isolation structure is after the step of forming embedded bit lines but before the step of forming embedded word lines in the semiconductor substrate.
13. The manufacturing method of the vertical channel transistor array as claimed in claim 1, wherein each of the bit line contacts being contacted with a side surface of the semiconductor pillar.