1. A semiconductor device comprising:
a plurality of vertical MOS transistors sharing a gate electrode of a first conductivity type, wherein said plurality of vertical MOS transistors comprises first semiconductor pillars with a first gate insulating film formed around lateral sides of the first semiconductor pillars, and the lateral sides of the first semiconductor pillars facing said gate electrode via said first gate insulating film; and
a second semiconductor pillar being of the first conductivity type with a second gate insulating film formed around lateral sides of the second semiconductor pillar, and being in contact with said gate electrode at a portion thereof from which at least a part of said second gate insulating film is removed, wherein potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected through said second semiconductor pillar.
2. The semiconductor device according to claim 1, wherein the potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected through an electrodeinterconnection contacted on the top of said second semiconductor pillar.
3. The semiconductor device according to claim 1, wherein the potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected through an electrodeinterconnection contacted with a diffusion layer of the first conductivity type formed at the bottom of said second semiconductor pillar.
4. The semiconductor device according to claim 1, wherein the potential supply to said gate electrode shared between said plurality of vertical MOS transistors is effected by driving a separate vertical MOS transistor which shares with said second semiconductor pillar a diffusion layer of the first conductivity type formed at the bottom of said second semiconductor pillar.
5. The semiconductor device according to claim 1, which includes an arrayed configuration wherein: a plurality of transistor columns is disposed each including said plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; and transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.
6. The semiconductor device according to claim 2, which includes an arrayed configuration wherein: a plurality of transistor columns are disposed each including a plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.
7. The semiconductor device according to claim 3, which includes an arrayed configuration wherein: a plurality of transistor columns are disposed each including a plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.
8. The semiconductor device according to claim 4, which includes an arrayed configuration wherein: a plurality of transistor columns are disposed each including a plurality of vertical MOS transistors sharing a gate electrode of the first conductivity type; transistors in a row each belonging to a respective one of the transistor columns are interconnected through a diffusion layer of the first conductivity type formed under each of the first semiconductor pillars in a row direction of each of the first semiconductor pillars intersecting the transistor columns, to form a bit line extending under the transistors in the row direction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus for filtering air in a vehicle, comprising, in combination:
a hinge mechanism for connecting a front panel, having an inside and an outside surface, of a conventional vent assembly to the remainder of the assembly;
at least a clip, disposed along an inside surface of the panel, to operatively position a filter member, and a filter member sized to substantially cover an inside surface of the front panel.
2. The apparatus of claim 1, further comprising a plurality of clips.
3. The apparatus of claim 1, further comprising at least two sets of opposing clips, arranged generally parallel at opposing locations along the inside surface of the panel.
4. A process for enhancing air quality in a passenger vehicle, comprising in combination:
providing a kit including a hinge and clip assembly and a universally adjustable air filter member effective to function in a conventional vent assembly; and
providing instructions for installing the kit within the vehicle.
5. A process for assembling a fresh venting improved system comprising, in combination:
modifying a venting mechanism, having a slotted panel, to render it hinged;
adding clips to a back side of the venting mechanism; for housing a filter member;
6. The process of claim 5, further comprising the step of emplacing the finished unit in a vehicle.
7. The process of claim 5, further comprising a vehicle with at least one of an existing vent and a set of vents.
8. Process of claim 5 further comprising a vehicle custom fitted for use fresh venting with a filter.