What is claimed is:
1. A synchronous semiconductor memory apparatus, comprising:
a first input circuit receiving a synchronous signal;
one or more second input circuits receiving a control signal; and
a plurality of third input circuits receiving input information including addresses or data for an access to individual memory cells,
a logic circuit receiving an output signal of the first input circuit and an output signal of at least any one of the one or more second input circuits as an input signal; and
first latch circuits for latching output signals of the third input circuits according to an output signal of the logic circuit.
2. A synchronous semiconductor memory apparatus according to claim 1, wherein the logic circuit comprises a detector circuit for detecting an output signal of the first input circuit and a logical computation circuit for checking that an output signal of at least any one of the second input circuits conforms to predetermined conditions when an output signal of the first input circuit is detected by means of the detector circuit, the first latch circuit comprises an activation circuit for activating a latch operation by inputting an output signal of the logical computation circuit, and output signals of the third input circuits are latched based on the fact that it is checked that the logical computation circuit conforms to the predetermined conditions to drive the activation circuit.
3. A synchronous semiconductor memory apparatus according to claim 1, wherein output signals of the third input circuits latched in the first latch circuits based on output signals of the first and second input circuits are input information including the addresses or data input to the third input circuits when the synchronous signal is input to the first input circuit, and the latch operation completes in one cycle of the synchronous signal.
4. A synchronous semiconductor memory apparatus according to claim 1, wherein the apparatus comprises second latch circuits for latching output signals of the second input circuits, and output signals of the second input circuits input to the logic circuit are output signals of the second latch circuits.
5. A synchronous semiconductor memory apparatus according to claim 1, wherein, of the third input circuits, address input circuits to which the addresses are input comprises row address latch circuits and column address latch circuits independently, and further comprises a row address logic circuit for controlling a latch operation of the row address latch circuits and a column address logic circuit for controlling a latch operation of the column address latch circuits independently.
6. A synchronous semiconductor memory apparatus according to claim 1, wherein the control signals input to the second input circuits are ICS, RAS, CAS, orWE.
7. A synchronous semiconductor memory apparatus according to claim 1, wherein an output signal of the logic circuit is directed to an active command, a read command, a write command, a pre-charge command, or a mode register set command.
8. A synchronous semiconductor memory apparatus according to claim 1, wherein the input information contains a write mask control signal, and the addresses contains a bank address.
9. A method for latching and controlling input information on a synchronous semiconductor memory apparatus comprising:
a synchronous signal input step of inputting a synchronous signal;
a control signal input step of inputting one or more control signals;
an information input step of inputting input information including addresses or data for an access to individual memory cells;
a logic step of receiving an output signal obtained in accordance with the synchronous signal input step and one or more output signals obtained in accordance with the control signal input step; and
a first latch step of latching output signals obtained in accordance with the information input step according to an output signal obtained in accordance with the logic step.
10. A method for latching and controlling input information on a synchronous semiconductor memory apparatus according to claim 9,
wherein the logic step comprises a detection step of detecting an output signal obtained in accordance with the synchronous signal input step; and a logical computation step of checking that one or more output signals obtained in accordance with the control signal input step conforms to predetermined conditions during the detection in accordance with the detecting step, and
the first latch step comprises a latch activation step of latching output signals obtained in accordance with the information input step based on the fact that an output signal obtained in accordance with the logical computation step conforms to predetermined conditions.
11. A method for latching and controlling input information on a synchronous semiconductor memory apparatus according to claim 9, wherein the first latch step completes a latch operation of the output signals obtained in accordance with the information input step performed in parallel to the synchronous signal input step within one cycle of the synchronous signal input step.
12. A method for latching and controlling input information on a synchronous semiconductor memory apparatus according to claim 9, wherein the latching and controlling method comprises a second latch step of latching the output signals obtained in accordance with the control signal input step, and the output signals obtained in accordance with the control signal input step to be input to the logic step are output signals obtained in accordance with the second latch step.
13. A method for latching and controlling input information on a synchronous semiconductor memory apparatus according to claim 9, wherein the first latch step is executed in accordance with a proper combination of ICS, RAS, CAS, andWE input in the control signal input step.
14. A method for latching and controlling input information on a synchronous semiconductor memory apparatus according to claim 9, wherein the first latch step is executed in the case where an output signal obtained in accordance with the logic step is an active command, a read command, a write command, a pre-charge command, or mode register set command.
15. A method for latching and controlling input information on a synchronous semiconductor memory apparatus according to claim 9, wherein the input information input in the information input step contains a write mask control signal, and the addresses contains a bank address.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device to measure viscosity changes of a sample, the device comprising:
a sample port fluidly coupled to a sample chamber;
a sample with changing viscosity in the sample chamber;
a field inductor inductively coupled to the sample;
a sensor inductor inductively coupled to the sample; and,
an electronic detector in electrical contact with the sensor inductor;
whereby induction of a voltage or current in the sensor inductor by the field inductor detectably varies as the sample viscosity changes, thereby measuring viscosity changes in the sample.
2. The device of claim 1, wherein the device is a microfluidic device.
3. The device of claim 1, wherein the sample is stationary in the sample chamber during the viscosity changes.
4. The device of claim 1, wherein the sample is in contact with a reagent that changes the viscosity of the sample.
5. The device of claim 1, wherein the detector measures a voltage, a current, a resistance or a phase shift in the sensor inductor.
6. A viscosity sensor comprising:
a field inductor;
a sensor inductor, separate from the field inductor; and,
a sample chamber comprising an electrically conductive sample of changing viscosity,
wherein the sample is inductively coupled to the field inductor and inductively coupled to the sensor inductor.
7. The sensor of claim 6, wherein the sample chamber is in a laminar cartridge and positioned in a sample layer having opposite parallel planar surfaces, and
wherein the field and sensor inductors are positioned on opposite sides of the sample layer.
8. The sensor of claim 6, wherein the sample chamber is tubular with a central axis, and wherein the field inductor or sensor inductor is a conductor coiled around the axis.
9. The sensor of claim 6, wherein the sample is selected from the group consisting of: a polymerizing plastic, blood, synovial fluid, placental fluid, CSF and plasma.
10. The sensor of claim 6, further comprising an electric field shield between the field inductor and sensor inductor.
11. The sensor of claim 6, further comprising a reagent in the sample chamber active in polymerizing or coagulating the conductive fluid.
12. A viscosity sensor comprising:
a first inductor;
a second inductor; and,
a sample chamber between the first and second inductive coils and inductively coupled to both the first and second inductors;
wherein the sample chamber has a volume less than 0.3 mm3 between the coils.
13. The sensor of claim 12, wherein the first inductor is inductively coupled to the second inductor.
14. The sensor of claim 12, further comprising an electric field shield between the first and second inductors.
15. The sensor of claim 12, wherein the sample chamber is positioned in a sample layer having opposite parallel planar surfaces, and the first and second inductors are positioned on opposite sides of the sample layer.
16. A sensor in a layered microfluidic cartridge, wherein the sensor comprises:
a field inductor in a first layer of the microfluidic cartridge;
a sample chamber in a second layer of the cartridge between the first layer and a third layer; and
a sensor inductor in the third layer of the cartridge;
wherein a conductive fluid in the sample chamber would be inductively coupled to the field inductor and to the sensor inductor.
17. The sensor of claim 16, wherein the field inductor or sensor inductor comprises a conductive material coiled within a plane substantially parallel to the second layer.
18. The sensor of claim 16, further comprising an electric field shield between the first and second inductors.
19. The sensor of claim 16, further comprising the conductive fluid in the sample chamber.
20. A sensor comprising:
a sample conduit having a central axis;
a field inductor of conductive material coiled around the sample conduit at a first position;
a sensor inductor of conductive material coiled around the sample conduit at a second position separated from the first position by a sample space distance along the axis;
a sample chamber in the conduit in the region of the sample space separation; and,
an electric field shield between the inductors, wherein the shield blocks electromagnetic field lines running between the field inductor and sensor inductor;
whereby a conductive fluid in the sample space would be inductively coupled to the field inductor and inductively coupled to the sensor inductor.
21. The sensor of claim 20, wherein the shield blocks electromagnetic field lines that run between the sensor inductor and field inductor without passing through the sample chamber sample space.
22. The sensor of claim 20, further comprising a detector in electrical contact with the field inductor or sensor inductor, which detector measures a parameter selected from the group consisting of: a voltage, a current, a waveform or a phase shift.
23. The sensor of claim 20, further comprising the conductive fluid in the sample chamber.
24. A sensor comprising:
a field inductor inductively coupled to a sample chamber comprising an inner surface;
one or more detector electrodes in electrical contact with the inner surface; and,
an electronic detector in electrical contact with the sample chamber surface through the detector electrodes;
whereby an electrical current induced by the inductor on a sample in the sample chamber is detected to determine a viscosity, a voltage, a current, a waveform or a phase shift in the sample.
25. A method of determining a viscosity of a conductive fluid, wherein the method comprises:
providing a sample chamber inductively coupled to a field inductor and to a sensor inductor;
providing a conductive fluid in the sample chamber;
providing an electronic detector in functional contact with the sensor inductor;
generating an electric field with the field inductor;
detecting with the detector an electric current or voltage induced in the sensor inductor by the electric field; and,
evaluating the detected current or voltage to determine the viscosity of the sample.
26. The method of claim 25, wherein the conductive fluid is selected from the group consisting of: whole blood, polymerizing plastic, synovial fluid, CSF, placental fluid and blood plasma.
27. The method of claim 25, wherein the electric current or voltage is induced or modulated by an electric field generated by a current flowing in the conductive fluid.
28. The method of claim 25, further comprising blocking electromagnetic lines of force between the first and second inductors, but not blocking lines through the sample chamber.
29. The method of claim 25, further comprising detecting a change in the viscosity of the fluid with time by detecting the current or voltage at two or more time points.
30. The method of claim 29, wherein the change in viscosity with time is detected while the fluid is not flowing.
31. The method of claim 25, wherein the field inductor is inductively coupled to the sensor inductor, and wherein said detecting comprises detecting modulation of a current induced by the field inductor in the sensor inductor, wherein said modulation results from induction of the sensor inductor by a current in the conductive fluid.
32. The method of claim 25, further comprising comparing the viscosity of the conductive fluid to a viscosity of a control fluid or to a reference standard.
33. The method of claim 25, wherein said evaluating comprises determining a phase shift between the field inductor and sensor inductor, or between the field inductor and the conductive fluid.
34. The method of claim 25, further comprising contacting the conductive fluid with a reagent that influences the viscosity or conductivity of the conductive fluid.