1. A method for call handover from a source cell associated with a first Base Transceiver Station (BTS), to a target cell associated with a second BTS in a telecommunications system in which the BTSs are directly connected to a Media Gateway (MGW) or via a transmission network including the steps of:
connecting the first BTS to a radio access termination (RAT) at the MGW; and
connecting the second BTS to the same RAT as the first BTS.
2. The method as claimed in claim 1 and including the steps of: the RAT multicasting the same voice flow towards the two BTS.
3. The method as claimed in claim 2 wherein the RAT multicasts either the same codec to each BTS or a different codec for each BTS.
4. The method as claimed in claim 1 and wherein the RAT transmits only one flow to a single BTS at a time if the codecs for the BTS are different and the RAT does not have sufficient resources to encode with two different codecs.
5. The method as claimed in claim 1 wherein signaling between the BTSs and the MGW uses Real time Transport Protocol, RTP.
6. The method as claimed in claim 1 wherein the telecommunications system is in accordance with 3GPP A-interface over IP, AoIP, specifications.
7. The method as claimed in claim 1 and including the step of the RAT switching to receive voice packets from the first to the second BTS on the reception of at least one valid speech block from the second BTS.
8. The method as claimed in claim 7 and including deciding which codec to use in the downlink direction, based on the reception of at least one valid speech block from the BTS.
9. The method as claimed in claim 7 and including using data from the BTS which sent the last voice packet to decide which uplink connection should be used for the uplink voice generation and which codec should be used for the downlink direction.
10. The method as claimed in claim 1 and wherein, in transcoder free operation, (TRFO), the RAT is provided by a BTS.
11. The method as claimed in claim 10 and wherein the telecommunications system is in accordance with 3GLTE specifications.
12. A telecommunications system comprising: a first Base Transceiver Station (BTS); a second Base Transceiver Station (BTS), a Media Gateway (MGW) and a radio access termination (RAT), operative such that, for call handover from a source cell associated with the first BTS to a target cell associated with the second BTS, the first BTS and second BTS are both connectable to the MGW at the same RAT.
13. The system as claimed in claim 12 and the RAT being operative to multicast the same voice flow towards the first BTS and second BTS.
14. The method as claimed in claim 12 wherein the RAT multicasts either the same codec to each BTS or a different codec for each BTS.
15. The system as claimed in claim 12 and wherein the RAT is arranged to transmit only one flow to a single BTS at a time if the codecs for the first BTS and second BTS are different and the RAT does not have sufficient resources to encode with two different codecs.
16. The system as claimed in claim 12 wherein signaling between the first BTS, the second BTS and the MGW uses Real time Transport Protocol (RTP).
17. The system as claimed in claim 12 and in accordance with 3GPP A-interface over IP, AoIP, specifications.
18. The system as claimed in claim 12 and the RAT being arranged to switch to receive voice packets from the first to the second BTS on the reception of at least one valid speech block from the second BTS.
19. The system as claimed in claim 12 and the RAT being arranged to select which codec to use in the downlink direction, based on the reception of at least one valid speech block from the second BTS.
20. The system as claimed in claim 12 and the RAT being arranged to use data from the BTS which sent the last voice packet to decide which uplink connection should be used for the uplink voice generation and which codec should be used for the downlink direction.
21. The system as claimed in claim 12 and wherein, in transcoder free operation, (TRFO) the RAT is provided by a BTS.
22. The system as claimed in claim 21 and being in accordance with 3GLTE specifications.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit structure comprising:
a conductive line;
a self-aligned dielectric layer on a sidewall of the conductive line;
an air-gap horizontally proximate the self-aligned dielectric layer, a horizontal plane intersecting the air-gap and the self-aligned dielectric layer;
a low-k dielectric layer horizontally proximate the air-gap, the horizontal plane intersecting the low-k dielectric layer; and
a dielectric layer on the air-gap and the low-k dielectric layer, a surface of the dielectric layer being parallel with the horizontal plane.
2. The integrated circuit structure of claim 1, wherein a top surface of the low-k dielectric layer levels with a top surface of the air-gap, and a bottom surface of the low-k dielectric layer levels with a bottom surface of the air-gap.
3. The integrated circuit structure of claim 1, wherein the self-aligned dielectric layer has a low-k value.
4. The integrated circuit structure of claim 1 further comprising:
an additional air-gap on an opposite side of the low-k dielectric layer from the air-gap;
an additional self-aligned dielectric layer proximate the additional air-gap, wherein the additional air-gap and the additional self-aligned dielectric layer are on a same level; and
an additional conductive line proximate the additional self-aligned dielectric layer.
5. The integrated circuit structure of claim 1, wherein the conductive line comprises a copper line on a diffusion barrier layer, and wherein the diffusion barrier layer physically contacts the self-aligned dielectric layer.
6. The integrated circuit structure of claim 1 further comprising:
an etch stop layer underlying the low-k dielectric layer and the air-gap, wherein the self-aligned dielectric layer has a bottom surface interfacing a top surface of the etch stop layer;
an additional low-k dielectric layer underlying the etch stop layer;
a via in the additional low-k dielectric layer and connected to the conductive line;
an additional self-aligned dielectric layer on a sidewall of the via; and
a first layer proximate the additional self-aligned dielectric layer and the additional low-k dielectric layer, wherein the first layer has a higher k value than k values of the additional self-aligned dielectric layer and the additional low-k dielectric layer.
7. The integrated circuit structure of claim 6, wherein the first layer has a lower carbon concentration than the additional self-aligned dielectric layer and the additional low-k dielectric layer.
8. The integrated circuit structure of claim 6, wherein the etch stop layer and the conductive line has a first interface, and wherein a second interface between the self-aligned dielectric layer and the conductive line is substantially vertically aligned to the first interface.
9. The integrated circuit structure of claim 1 further comprising:
an additional low-k dielectric layer underlying the air-gap and the low-k dielectric layer, wherein the additional low-k dielectric layer and the low-k dielectric layer are portions of a continuous layer;
a via in the additional low-k dielectric layer and connected to the conductive line;
an additional self-aligned dielectric layer on a sidewall of the via; and
a damaged layer proximate the additional self-aligned dielectric layer and the additional low-k dielectric layer, wherein the damaged layer has a higher k value than k values of the additional self-aligned dielectric layer and the additional low-k dielectric layer, and wherein the air-gap extends into a top portion of the damaged layer.
10. An integrated circuit structure comprising:
a first conductive line disposed in a low-k dielectric layer;
a first dielectric layer on a first sidewall of the first conductive line;
a second dielectric layer on a second sidewall of the first conductive line opposite from the first sidewall;
a first air-gap disposed between the first dielectric layer and a first portion of the low-k dielectric layer; and
a second air-gap disposed between the first dielectric layer and a second portion of the low-k dielectric layer, wherein the first conductive line, the first air gap, the second air-gap, the first dielectric layer, the second dielectric layer, the first portion of the low-k dielectric, and the second portion of the low-k dielectric layer intersect a plane.
11. The integrated circuit of claim 10 further comprising:
a second conductive line intersecting the plane;
a third dielectric layer on a sidewall of the second conductive line;
a third air-gap disposed between the third dielectric layer and the second portion of the low-k dielectric layer, wherein the third dielectric layer is disposed between the third air-gap and the second conductive line.
12. The integrated circuit structure of claim 10 further comprising an etch stop layer underlying the low-k dielectric layer and the first air-gap and the second air-gap, wherein the first dielectric layer and the second dielectric layer each have a bottom surface contacting a top surface of the etch stop layer.
13. The integrated circuit structure of claim 12, wherein the etch stop layer and the first conductive line has a first interface, and wherein a second interface between the first dielectric layer and the first conductive line is substantially vertically aligned to the first interface.
14. The integrated circuit structure of claim 10 further comprising:
an additional low-k dielectric layer under the low-k dielectric layer; and
a via connected to the first conductive line and disposed in the additional low-k dielectric layer, wherein the first air gap extends into the additional low-k dielectric layer.
15. The integrated circuit structure of claim 10 further comprising a third dielectric layer over the first air-gap, the second air-gap, and the low-k dielectric layer.
16. An integrated circuit structure comprising:
a first low-k dielectric layer;
a via in the first low-k dielectric layer;
a first self-aligned dielectric layer on a sidewall of the via;
a first layer proximate the first self-aligned dielectric layer and the first low-k dielectric layer, wherein the first layer has a higher k value than the first self-aligned dielectric layer and the first low-k dielectric layer;
a second low-k dielectric layer over the first low-k dielectric layer;
a conductive line in the second low-k dielectric layer and contacting the via;
a second self-aligned dielectric layer on a sidewall of the conductive line;
an air-gap horizontally proximate the second self-aligned dielectric layer and the second low-k dielectric layer; and
a first etch stop layer on the air-gap and the second low-k dielectric layer.
17. The integrated circuit structure of claim 16 further comprising a second etch stop layer between the first and the second low-k dielectric layers.
18. The integrated circuit structure of claim 16, wherein the first and the second low-k dielectric layers are portions of a continuous layer, and wherein the air-gap extends into a top portion of the first layer.
19. The integrated circuit structure of claim 16 further comprising:
an additional conductive line underlying and connected to the via;
a third self-aligned dielectric layer on a sidewall of the additional conductive line;
an additional air-gap horizontally proximate the third self-aligned dielectric layer; and
a third low-k dielectric layer horizontally proximate the air-gap.
20. The integrated circuit structure of claim 16 further comprising:
an additional conductive line in the second low-k dielectric layer;
a third self-aligned dielectric layer on a sidewall of the additional conductive line; and
an additional air-gap horizontally proximate the third self-aligned dielectric layer and the second low-k dielectric layer.