1. A method for transmitting data in a communication or broadcasting system, comprising:
generating a codeword by encoding input information data bits;
interleaving the codeword;
demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
outputting a modulation signal by modulating the demultiplexed bits; and
transmitting the modulation signal,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2155 and \xbc, the bit-mapping table is defined as:
16-QAM
Input bit number
0
1
2
3
4
5
6
7
Output bit number
1
7
0
5
4
2
6
3
where the \u201cinput bit number\u201d represents an input bit number di in the interleaved codeword vd, and the \u201coutput bit number\u201d represents a demultiplexed substream value e in the demultiplexed bits be,d0.
2. A method for transmitting data in a communication or broadcasting system, comprising:
generating a codeword by encoding input information data bits;
interleaving the codeword;
demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
outputting a modulation signal by modulating the demultiplexed bits; and
transmitting the modulation signal,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2153 and 512, the bit-mapping table is defined as:
16-QAM
Input bit number
0
1
2
3
4
5
6
7
Output bit number
7
1
2
5
4
0
6
3
where the \u201cinput bit number\u201d represents an input bit number di in the interleaved codeword vd, and the \u201coutput bit number\u201d represents a demultiplexed substream value e in the demultiplexed bits be,d0.
3. A method for transmitting data in a communication or broadcasting system, comprising:
generating a codeword by encoding input information data bits;
interleaving the codeword;
demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
outputting a modulation signal by modulating the demultiplexed bits; and
transmitting the modulation signal,
wherein outputting modulation signal-constituting bits comprises bit-mapping the interleaved codeword using a different bit-mapping scheme depending on a ratio of lowest-degree bits to all bits constituting the interleaved codeword.
4. A method for transmitting data in a communication or broadcasting system, comprising:
generating a codeword by encoding input information data bits;
interleaving the codeword;
demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
outputting a modulation signal by modulating the demultiplexed bits; and
transmitting the modulation signal,
wherein demultiplexing the interleaved codeword comprises bit-mapping the interleaved codeword using a different bit-mapping scheme depending on at least one of a degree distribution of a parity check matrix and positions of columns of an information part of the parity check matrix.
5. An apparatus for transmitting data in a communication or broadcasting system, comprising:
an encoder for generating a codeword by encoding input information data bits;
an interleaver for interleaving the codeword;
a demultiplexer for demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
a modulator for outputting a modulation signal by modulating the demultiplexed bits; and
a transmitter for transmitting the modulation signal,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2155 and \xbc, the bit-mapping table is defined as:
16-QAM
Input bit number
0
1
2
3
4
5
6
7
Output bit number
1
7
0
5
4
2
6
3
where the \u201cinput bit number\u201d represents an input bit number di in the interleaved codeword vd, and the \u201coutput bit number\u201d represents a demultiplexed substream value e in the demultiplexed bits be,d0.
6. An apparatus for transmitting data in a communication or broadcasting system, comprising:
an encoder for generating a codeword by encoding input information data bits;
an interleaver for interleaving the codeword;
a demultiplexer for demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
a modulator for outputting a modulation signal by modulating the demultiplexed bits; and
a transmitter for transmitting the modulation signal,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2153 and 512, the bit-mapping table is defined as:
16-QAM
Input bit number
0
1
2
3
4
5
6
7
Output bit number
7
1
2
5
4
0
6
3
where the \u201cinput bit number\u201d represents an input bit number di in the interleaved codeword vd, and the \u201coutput bit number\u201d represents a demultiplexed substream value e in the demultiplexed bits be,d0.
7. An apparatus for transmitting data in a communication or broadcasting system, comprising:
an encoder for generating a codeword by encoding input information data bits;
an interleaver for interleaving the codeword;
a demultiplexer for demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
a modulator for outputting a modulation signal by modulating the demultiplexed bits; and
a transmitter for transmitting the modulation signal,
wherein the demultiplexer demultiplexes the interleaved codeword using a different bit-mapping scheme depending on a ratio of lowest-degree bits to all bits constituting the interleaved codeword.
8. An apparatus for transmitting data in a communication or broadcasting system, comprising:
an encoder for generating a codeword by encoding input information data bits;
an interleaver for interleaving the codeword;
a demultiplexer for demultiplexing the interleaved codeword using a bit-mapping table that is determined based on a modulation scheme and a coding rate;
a modulator for outputting a modulation signal by modulating the demultiplexed bits; and
a transmitter for transmitting the modulation signal,
wherein the demultiplexer demultiplexes the interleaved codeword using a different bit-mapping scheme depending on at least one of a degree distribution of a parity check matrix and positions of columns of an information part of the parity check matrix.
9. A method for receiving data in a communication or broadcasting system, comprising:
receiving a signal transmitted by a transmitter;
demodulating the received signal;
multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
deinterleaving the multiplexed bits; and
decoding the deinterleaved bits,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2155 and \xbc, the bit-mapping table is defined as:
16-QAM
Output bit number
0
1
2
3
4
5
6
7
Input bit number
1
7
0
5
4
2
6
3
where the \u201coutput bit number\u201d represents an output bit number di in an interleaved codeword vd, by the transmitter, and the \u201cinput bit number\u201d represents a received substream value e in the demodulated bits be,d0.
10. A method for receiving data in a communication or broadcasting system, comprising:
receiving a signal transmitted by a transmitter;
demodulating the received signal;
multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
deinterleaving the multiplexed bits; and
decoding the deinterleaved bits,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2153 and 512, the bit-mapping table is defined as:
16-QAM
Output bit number
0
1
2
3
4
5
6
7
Input bit number
7
1
2
5
4
0
6
3
where the \u201coutput bit number\u201d represents an output bit number di in an interleaved codeword vd, by the transmitter, and the \u201cinput bit number\u201d represents a received substream value e in the demodulated bits be,d0.
11. A method for receiving data in a communication or broadcasting system, comprising:
receiving a signal transmitted by a transmitter;
demodulating the received signal;
multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
deinterleaving the multiplexed bits; and
decoding the deinterleaved bits,
wherein multiplexing comprises multiplexing the demodulated signal using a different multiplexing scheme depending on a ratio of lowest-degree bits to all bits constituting an interleaved codeword by the transmitter.
12. A method for receiving data in a communication or broadcasting system, comprising:
receiving a signal transmitted by a transmitter;
demodulating the received signal;
multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
deinterleaving the multiplexed bits; and
decoding the deinterleaved bits,
wherein multiplexing comprises multiplexing the demodulated signal using a different multiplexing scheme depending on at least one of a degree distribution of a parity check matrix and positions of columns of an information part of the parity check matrix.
13. An apparatus for receiving data in a communication or broadcasting system, comprising:
a receiver for receiving a signal transmitted by a transmitter;
a demodulator for demodulating the received signal;
a multiplexer for multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
a deinterleaver for deinterleaving the multiplexed bits; and
a decoder for decoding the deinterleaved bits,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2155 and \xbc, the bit-mapping table is defined as:
16-QAM
Output bit number
0
1
2
3
4
5
6
7
Input bit number
1
7
0
5
4
2
6
3
where the \u201coutput bit number\u201d represents an output bit number di in an interleaved codeword vd by the transmitter, and the \u201cinput bit number\u201d represents a received substream value e in the demodulated bits be,d0.
14. An apparatus for receiving data in a communication or broadcasting system, comprising:
a receiver for receiving a signal transmitted by a transmitter;
a demodulator for demodulating the received signal;
a multiplexer for multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
a deinterleaver for deinterleaving the multiplexed bits; and
a decoder for decoding the deinterleaved bits,
wherein when the modulation scheme is 16-Quadrature Amplitude Modulation (16-QAM) and the coding rate includes one of \u2153 and 512, the bit-mapping table is defined as:
16-QAM
Output bit number
0
1
2
3
4
5
6
7
Input bit number
7
1
2
5
4
0
6
3
where the \u201coutput bit number\u201d represents an output bit number d, in an interleaved codeword vd by the transmitter, and the \u201cinput bit number\u201d represents a received substream value e in the demodulated bits be,d0.
15. An apparatus for receiving data in a communication or broadcasting system, comprising:
a receiver for receiving a signal transmitted by a transmitter;
a demodulator for demodulating the received signal;
a multiplexer for multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
a deinterleaver for deinterleaving the multiplexed bits; and
a decoder for decoding the deinterleaved bits,
wherein the multiplexer multiplexes the demodulated signal using a different bit-demapping scheme depending on a ratio of lowest-degree bits to all bits constituting an interleaved codeword by the transmitter.
16. An apparatus for receiving data in a communication or broadcasting system, comprising:
a receiver for receiving a signal transmitted by a transmitter;
a demodulator for demodulating the received signal;
a multiplexer for multiplexing the demodulated signal using a bit-mapping table that is determined based on a modulation scheme and a coding rate of the transmitter;
a deinterleaver for deinterleaving the multiplexed bits; and
a decoder for decoding the deinterleaved bits,
wherein the bit multiplexer multiplexes the demodulated signal using a different bit-demapping scheme depending on at least one of a degree distribution of a parity check matrix and positions of columns of an information part of the parity check matrix.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power supply apparatus including:
a boosting circuit which boosts power supply voltage at a preset boosting rate and outputs drive voltage of a device;
a regulator circuit which adjusts input voltage to said boosting circuit in order for a detected voltage of an output line in said boosting circuit to be equal to a reference voltage;
a power supply voltage detecting circuit which detects the power supply voltage supplied to said regulator circuit; and
a boosting rate switching circuit which supplies, based on the detected power supply voltage, a signal by which to switch the boosting rate to said boosting circuit,
wherein said boosting circuit, said regulator circuit, said power supply voltage detecting circuit and said boosting rate switching circuit are monolithically integrated.
2. A power supply apparatus according to claim 1, wherein said boosting circuit is structured in a manner such that the boosting rate is switchable in multiple stages and wherein said boosting rate switching circuit sends to said boosting circuit a signal by which to switch the boosting rate stepwise.
3. A power supply apparatus according to claim 2, wherein when the detected power supply voltage becomes lower than a predetermined reference voltage, said boosting rate switching circuit sends to said boosting circuit a switching signal to raise the boosting rate.
4. A power supply apparatus according to claim 2, wherein when the detected power supply voltage becomes higher than a predetermined reference voltage, said boosting rate switching circuit sends to said boosting circuit a switching signal to lower the boosting rate.
5. A power supply apparatus according to claim 2, wherein said boosting circuit boosts the power supply voltage at the boosting rate by selectively charging or discharging a plurality of boosting capacitors.
6. A power supply apparatus including:
a boosting circuit which boosts power supply voltage at a preset boosting rate and outputs drive voltage of a device;
a regulator circuit which adjusts input voltage to said boosting circuit in order for a detected voltage of an output line in said boosting circuit to be equal to a reference voltage;
a terminal voltage detecting circuit which detects terminal voltage of the device which is connected to an output terminal of said boosting circuit as a load; and
a boosting rate switching circuit which supplies, based on the detected terminal voltage, a signal by which to switch the boosting rate to said boosting circuit,
wherein said boosting circuit, said regulator circuit, said terminal voltage detecting circuit and said boosting rate switching circuit are monolithically integrated.
7. A power supply apparatus according to claim 6, wherein said terminal voltage detecting circuit detects terminal voltage of each of a plurality of devices connected to the output terminal of said boosting circuit as a load and wherein said boosting rate switching circuit includes: a plurality of comparators which compare the terminal voltage of each of the devices with a predetermined threshold value; and a logic circuit which evaluates outputs from the plurality of comparators by a predetermined logic operation and which, based on the evaluation result, supplies a signal by which to switch the boosting rate to said boosting circuit.
8. A power supply apparatus according to claim 7, wherein said boosting circuit is structured in a manner such that the boosting rate is switchable in multiple stages and wherein said boosting rate switching circuit sends to said boosting circuit a signal by which to switch the boosting rate stepwise.
9. A power supply apparatus according to claim 8, wherein when at least one of the terminal voltages detected in the plurality of devices becomes lower than a predetermined reference voltage, said boosting rate switching circuit sends to said boosting circuit a switching signal to raise the boosting rate.
10. A power supply apparatus according to claim 8, wherein said boosting circuit boosts the power supply voltage at the boosting rate by selectively charging or discharging a plurality of boosting capacitors.
11. A power supply apparatus including:
a boosting circuit which boosts power supply voltage at a preset boosting rate and outputs drive voltage of a device;
a regulator circuit which adjusts input voltage to said boosting circuit in order for a detected voltage of an output line in said boosting circuit to be equal to a reference voltage;
a load current detecting circuit which detects load current of the device which is connected to an output terminal of said boosting circuit as a load; and
a boosting rate switching circuit which supplies, based on the detected load current, a signal by which to switch the boosting rate to said boosting circuit,
wherein said boosting circuit, said regulator circuit, said load current detecting circuit and said boosting rate switching circuit are monolithically integrated.
12. A power supply apparatus according to claim 11, wherein said load current detecting circuit detects load current of each of a plurality of devices connected to the output terminal of said boosting circuit as a load and wherein said boosting rate switching circuit includes: a plurality of comparators which compare the load current of each of the devices with a predetermined threshold value; and a logic circuit which evaluates outputs from the plurality of comparators by a predetermined logic operation and which, based on the evaluation result, supplies a signal by which to switch the boosting rate to said boosting circuit.
13. A power supply apparatus according to claim 12, wherein said boosting circuit is structured in a manner such that the boosting rate is switchable in multiple stages and wherein said boosting rate switching circuit sends to said boosting circuit a signal by which to switch the boosting rate stepwise.
14. A power supply apparatus according to claim 13, wherein when at least one of the load currents detected in the plurality of devices exceeds a prescribed value, said boosting rate switching circuit sends to said boosting circuit a switching signal to raise the boosting rate.
15. A power supply apparatus according to claim 13, wherein said boosting circuit boosts the power supply voltage at the boosting rate by selectively charging or discharging a plurality of boosting capacitors.
16. A power supply apparatus including:
a boosting circuit which boosts power supply voltage at a preset boosting rate and outputs drive voltage of a device;
a regulator circuit which adjusts input voltage to said boosting circuit in order for a detected voltage of an output line in said boosting circuit to be equal to a reference voltage;
a power supply voltage detecting circuit which detects the power supply voltage supplied to said regulator circuit;
a load current detecting circuit which detects load current of the device which is connected to an output terminal of said boosting circuit as a load; and
a boosting rate switching circuit which supplies, based on at least one of the detected power supply voltage and the detected load current, a signal by which to switch the boosting rate to said boosting circuit,
wherein said boosting circuit, said regulator circuit, said power supply voltage detecting circuit, said load current detecting circuit and said boosting rate switching circuit are monolithically integrated.
17. A power supply apparatus according to claim 16, wherein said boosting circuit is structured in a manner such that the boosting rate is switchable in multiple stages and wherein said boosting rate switching circuit sends to said boosting circuit a signal by which to switch the boosting rate stepwise.
18. A power supply apparatus according to claim 17, wherein when the detected power supply voltage becomes lower than a predetermined reference voltage or when the detected load current exceeds a prescribed value, said boosting rate switching circuit sends to said boosting circuit a switching signal to raise the boosting rate.
19. A power supply apparatus according to claim 17, wherein said boosting circuit boosts the power supply voltage at the boosting rate by selectively charging or discharging a plurality of boosting capacitors.