1. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the insulation layers; and
a conductor on the insulation layers, wherein a first portion of the conductor is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than 200 nm.
2. The device of claim 1, wherein the first portion of the conductor forms a first portion of the field plate.
3. The device of claim 2, wherein the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer.
4. The device of claim 3, wherein a second portion of the conductor forms a second portion of the field plate and is spaced apart from the 2DEG inducing layer by the insulation layers by a distance greater than 200 nm.
5. The device of claim 1, further comprising a capacitor, wherein the first portion of the conductor forms at least a portion of a plate of the capacitor.
6. The device of claim 1, further comprising a diode having a field plate, wherein the first portion of the conductor forms at least a portion of the field plate of the diode.
7. The device of claim 1, further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
8. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, wherein at least one of the insulation layers contacts the 2DEG inducing layer, and wherein at least one of the insulation layers comprises an opening; and
a conductor having a first portion in the opening, wherein the first portion of the conductor contacts the at least one insulation layer which contacts the 2DEG inducing layer.
9. The device of claim 8, wherein the first portion of the conductor forms a first portion of the field plate.
10. The device of claim 9, wherein the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer.
11. The device of claim 10, wherein a second portion of the conductor forms a second portion of the field plate and is spaced apart from the 2DEG inducing layer by the insulation layers by a distance greater than 200 nm.
12. The device of claim 8, further comprising a capacitor, wherein the first portion of the conductor forms at least a portion of the plate of the capacitor.
13. The device of claim 8, further comprising a diode having a field plate, wherein the first portion of the conductor forms at least a portion of the field plate of the diode.
14. The device of claim 8, wherein the first portion of the conductor is spaced apart from the 2DEG inducing layer by the at least one insulation layer which contacts the 2DEG inducing layer by a distance less than or equal to 200 nm.
15. The device of claim 8, further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
16. A semiconductor device, comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact; and
one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer.
17. The device of claim 16, further comprising a capacitor, wherein a plate of the capacitor is spaced apart from the 2DEG inducing layer by the insulation layers.
18. The device of claim 16, further comprising a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the insulation layers.
19. The device of claim 16, wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than or equal to 200 nm.
20. The device of claim 19, wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the insulation layers by a distance greater than 200 nm.
21. The device of claim 16, further comprising a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the second insulation layer.
22. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the insulation layers; and
a conductor on the insulation layers, wherein a first portion of the conductor is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than 200 nm.
23. The component of claim 22, wherein the first portion of the conductor forms a first portion of the field plate.
24. The component of claim 22, wherein the electronic circuit further comprises a capacitor, wherein the first portion of the conductor forms at least a portion of a plate of the capacitor.
25. The component of claim 22, wherein the electronic circuit further comprises a diode having a field plate, wherein the first portion of the conductor forms at least a portion of the field plate of the diode.
26. The component of claim 22, wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
27. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact;
one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, wherein at least one of the insulation layers contacts the 2DEG inducing layer, and wherein at least one of the insulation layers comprises an opening; and
a conductor having a first portion in the opening, wherein the first portion of the conductor contacts the at least one insulation layer which contacts the 2DEG inducing layer.
28. The component of claim 27, wherein the first portion of the conductor forms a first portion of the field plate.
29. The component of claim 27, wherein the electronic circuit further comprises a capacitor, wherein the first portion of the conductor forms at least a portion of a plate of the capacitor.
30. The component of claim 27, wherein the electronic circuit further comprises a diode having a field plate, wherein the first portion of the conductor forms at least a portion of the field plate of the diode.
31. The component of claim 27, wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
32. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a substrate comprising GaN;
a two dimensional electron gas (2DEG) inducing layer on the substrate;
a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
source and drain contacts to the 2DEG inducing layer,
a gate stack between the source and drain contacts, and
a field plate between the gate and the drain contact; and
one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer.
33. The component of claim 32, further comprising a capacitor, wherein a plate of the capacitor is spaced apart from the 2DEG inducing layer by the insulation layers.
34. The component of claim 32, further comprising a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the insulation layers.
35. The component of claim 32, wherein the first portion of the field plate is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than or equal to 200 nm.
36. The component of claim 32, wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the insulation layers by a distance greater than 200 nm.
37. The component of claim 32, wherein the electronic circuit further comprises a conductive gate contact contacting the gate stack, wherein the one or more insulation layers comprises first and second insulation layers, wherein a portion of the gate contact is spaced apart from the first insulation layer by the second insulation layer, and wherein the at least one insulation layer which contacts the 2DEG inducing layer is the second insulation layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of fabricating an exhaust washed composite structure comprising:
providing a corrugated septum comprised of a ceramic matrix composite (CMC) material extending in a lengthwise direction;
curing the corrugated septum;
positioning a bulk acoustic absorber so as to be interspersed with convolutes of the corrugated septum;
forming a flute of CMC material; and
disposing the corrugated septum following curing and the bulk acoustic absorber within the flute to form a partitioned flute assembly.
2. A method according to claim 1 wherein positioning the bulk acoustic absorber comprises rigidizing the bulk acoustic absorber and bonding rigidized blocks of the bulk acoustic absorber to the corrugated septum.
3. A method according to claim 1 further comprising disposing a plurality of partitioned flute assemblies between first and second face sheets.
4. A method according to claim 1 further comprising bonding the corrugated septum within the flute.
5. A method according to claim 1 wherein disposing the corrugated septum within the flute forms a partitioned CMC flute assembly.
6. A method according to claim 5 wherein the partitioned CMC flute assembly has radiused corner portions.
7. A method according to claim 1 further comprising providing the bulk acoustic absorber comprised of a non-rigid material.
9. A method according to claim 1 further comprising providing the bulk acoustic absorber comprised of a ceramic material.
9. A method according to claim 1 wherein forming the flute comprises forming the flute so as to define at least one perforation to establish fluid communication between the corrugated septum and the bulk acoustic absorber and an external environment.
10. A method of fabricating an exhaust washed structure comprising:
providing a wall member; and
positioning a plurality of partitioned flute assemblies upon the wall member and laterally adjacent another partitioned flute assembly so that each partitioned flute assembly extends lengthwise along the wall member, wherein each partitioned flute assembly comprises:
a corrugated septum comprised of a ceramic matrix composite (CMC) material extending lengthwise; and
a flute of CMC material having the corrugated septum disposed therein.
11. A method according to claim 10 wherein the wall member defines a plurality of sections spaced lengthwise therealong, wherein positioning the plurality of partitioned flute assemblies upon the wall member comprises positioning a plurality of partitioned flute assemblies upon each section of the wall member so that each partitioned flute assembly extends lengthwise along the respective section of the wall member, and wherein each partitioned flute assembly is positioned laterally adjacent another partitioned flute assembly within the respective section of the wall member.
12. A method according to claim 10 further comprising providing the plurality of partitioned flute assemblies with each partitioned flute assembly changing in lateral width in a lengthwise direction.
13. A method according to claim 10 further comprising providing the plurality of partitioned flute assemblies with each partitioned flute assembly further comprising a bulk acoustic absorber disposed proximate the corrugated septum and within the respective flute.
14. A method according to claim 13 wherein the bulk acoustic absorber is interspersed with convolutes of the corrugated septum.
15. A method according to claim 13 wherein the bulk acoustic absorber is comprised of a non-rigid material.
16. A method according to claim 13 wherein the bulk acoustic absorber is comprised of a ceramic material.
17. A method according to claim 10 further comprising providing the plurality of partitioned flute assemblies with each partitioned flute assembly in lateral cross-section having radiused corner portions.
18. A method according to claim 10 further comprising establishing fluid communication between the corrugated septum and the external environment via at least one perforation defined by the wall member and the flute.