1. An interior part mounting clip for mounting an interior part on a panel member, comprising:
a pin portion having a smaller external diameter than He an internal diameter of a mounting hole formed in a frame-shaped mounting seat formed on the interior part.
the pin portion being inserted into and movable in the mounting hole of the frame-shaped mounting seat:
a head portion being formed at one end of the pin portion, the head portion engaging with the mounting seat and including:
at least three protrusions protruding radially outward of the pin portion; and
an outer frame mounted to be elastically displacable relative to the pin portion through a plurality of elastic portions extending radially outward from at least part of the pin portion which is positioned among the at least three protrusions an outer circumference of the outer frame abutting against an inner circumference of the frame-shaped mounting seat and engaging with a circumferential edge of the mounting hole, and
a stem portion formed at the other end of the pin portion and engaging with an engaging hole formed in the panel member.
2. The interior part mounting clip according to claim 1, wherein the protrusions of the head portion and the elastic portions are protruded radially outward through a head flange portion protruding radially outward of the pin portion.
3. The interior part mounting clip according to claim 2, wherein a height of a side of each elastic portion to face the interior part, when each elastic portion is engaged with the mounting seat, is smaller than a height of the head flange portion and the outer frame.
4. The interior part mounting clip according to claim 2, wherein a height of a side of each protrusion to face the interior part, when each protrusion is engaged with the mounting seat, is smaller than a height of the head flange portion.
5. The interior part mounting clip according to claim 3, wherein a height of a side of each protrusion to face the interior part, when each protrusion is engaged with the mounting seat, is smaller than a height of the head flange portion.
6. The interior part mounting clip according to claim 1, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion, when the head portion engages with the mounting seat, is defined by a following expression:
L=A\u2212B+C,
wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion, when each engaging portion engages with the mounting hole is defined by C.
7. The interior part mounting clip according to claim 2, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion when the head portion engages with the mounting seat is defined by a following expression:
L=A\u2212B+C.
wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion, when each engaging portion engages with the mounting hole, is defined by C.
8. The interior part mounting clip according to claim 3, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion, when the head portion engages with the mounting seat, is defined by a following expression:
L=A\u2212B+C.
wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion when each engaging portion engages with the mounting hole, is defined by C.
9. The interior part mounting clip according to claim 4, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion, when the head portion engages with the mounting seat is defined by a following expression:
L=A\u2212B+C.
wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion, when each engaging portion engages with the mounting hole, is defined by C.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. An integrated circuit, comprising:
a plurality of cells;
an electrical bus in electrical communication with said plurality of cells, said electrical bus designed using a current distribution modeled prior to arrangement of said plurality of cells, said electrical bus comprising:
a region; and
a first metal layer containing a plurality of first wires extending in a first direction, each of said plurality of first wires having a first width at least partially located within said region;
wherein said first widths vary as a function of said current distribution.
2. An integrated circuit according to claim 1, wherein said region is rectangular in shape and has an axis of symmetry, each of said plurality of first wires being parallel to said axis of symmetry.
3. An integrated circuit according to claim 2, wherein said first widths of said plurality of first wires generally decrease toward said axis of symmetry.
4. An integrated circuit according to claim 3, wherein said first widths decrease logarithmically toward said axis of symmetry.
5. An integrated circuit according to claim 1, further comprising a second metal layer containing a plurality of second wires extending in a second direction different from said first direction, said plurality of second wires electrically coupled to said plurality of first wires, each of said plurality of second wires having a second width at least partially located within said region, said second widths varying in proportion to said current distribution.
6. An integrated circuit according to claim 5, wherein said region is rectangular in shape and has a first axis of symmetry and a second axis of symmetry, each of said plurality of first wires being parallel to said first axis of symmetry and each of said plurality of second wires being parallel to said second axis of symmetry.
7. An integrated circuit according to claim 6 wherein said first widths generally decrease toward said first axis of symmetry and said second widths generally decrease toward said second axis of symmetry.
8. An integrated circuit according to claim 7, wherein said first widths decrease logarithmically toward said first axis of symmetry and said second widths decrease logarithmically toward said second axis of symmetry.
9. A device, comprising:
a semiconductor chip containing a plurality of cells and having at least one electrical bus designed using a current distribution modeled prior to arrangement of said plurality of cells, said semiconductor chip comprising:
an area array of electrical contacts; and
a plurality of regions defined by said area array, each of said plurality of regions containing a first metal layer having a plurality of first wires extending in a first direction and electrically coupled to said electrical contacts, each of said plurality of first wires having a first width;
wherein said first widths of said first wires vary in each of said plurality of regions as a function of said current distribution; and
a power supply in electrical communication with said semiconductor chip.
10. A device according to claim 9, wherein said plurality of first wires in a first of said plurality of regions is identical to said plurality of first wires in others of said plurality of regions.
11. A device according to claim 9, wherein said plurality of first wires are linear and each of said plurality of regions is rectangular in shape and has an axis of symmetry parallel to each of said plurality of first wires.
12. A device according to claim 11, wherein said first widths of said plurality of first wires generally decrease toward said axis of symmetry.
13. A device according to claim 12, wherein said first widths decrease logarithmically toward said axis of symmetry.
14. A device according to claim 9, wherein each of said plurality of regions further comprises a second metal layer containing a plurality of second wires extending in a second direction different from said first direction, each of said plurality of second wires electrically coupled to said electrical contacts and having a second width, said second widths varying in proportion to said current distribution.
15. A device according to claim 14, wherein each of said plurality of first wires is linear and each of said plurality of second wires is linear, each of said plurality of regions being rectangular in shape and having a first axis of symmetry parallel to each of said plurality of first wires and a second axis of symmetry parallel to each of said plurality of second wires.
16. A device according to claim 15 wherein said first widths generally decrease toward said first axis of symmetry and said second widths generally decrease toward said second axis of symmetry.
17. A device according to claim 16, wherein said first widths decrease logarithmically toward said first axis of symmetry.
18. A device according to claim 16, wherein said second widths decrease logarithmically toward said second axis of symmetry.
19. A method of laying out an electrical bus grid of an integrated circuit having a plurality of regions, comprising in sequence the steps of:
arranging at least a plurality of first wires of a first metal layer in at least one of the plurality of regions, each of said plurality of first wires having a first width;
determining a current distribution among at least said plurality of first wires;
varying at least said first widths of said plurality of first wires as a function of said current distribution; and
arranging a plurality of cells to at least partially form the integrated circuit.
20. A method according to claim 19, wherein the step of arranging said plurality of first wires includes selecting a pattern of said plurality of first wires and repeating said pattern for at least some of the plurality of regions.
21. A method according to claim 19, wherein the step of determining current distribution includes modeling said plurality of wires as resistors.
22. A method according to claim 19, wherein the area array of electrical contacts is a rectangular array such that each of said plurality of regions has an axis of symmetry, said step of arranging said plurality of wires including arranging said plurality of wires so they are parallel to said axis of symmetry and said step of varying said first widths includes decreasing said first widths toward said axis of symmetry.
23. A method according to claim 22, wherein said step of varying said first widths includes decreasing said first widths logarithmically toward said axis of symmetry.
24. A method according to claim 19, wherein the step of arranging at least a plurality of first wires further includes arranging a plurality of second wires of a second metal layer in said at least one of the plurality of regions, each of said plurality of second wires having a second width, the step of determining a current distribution among at least a plurality of first wires includes determining a current distribution among at least said plurality of first wires and said plurality of second wires, and the step of varying at least said first widths of said plurality of first wires includes varying said first widths of said plurality of first wires and said second widths of said plurality of second wires as a function of said current distribution.
25. A method according to claim 24, wherein said at least one of the plurality of regions has an axis of symmetry parallel to said plurality of first wires and the step of varying at least said first widths includes decreasing said first widths logarithmically toward said axis of symmetry.
26. A method according to claim 24, wherein said at least one of the plurality of regions has an axis of symmetry parallel to said plurality of second wires and the step of varying at least said second widths includes decreasing said second widths logarithmically toward said axis of symmetry.
27. An integrated circuit having a plurality of cells, comprising:
a plurality of electrical contacts;
an electrical bus grid formed among said plurality of electrical contacts, said bus grid comprising:
a first metal layer;
a second metal layer spaced from said first metal layer;
a plurality of first wires located in said first metal layer and extending in a first direction; and
a plurality of second wires located in said second metal layer and extending in a second direction different from said first direction so as to form a crisscross pattern with said plurality of first wires;
wherein at least one of said plurality of first wires and said plurality of second wires contain wires having widths that differ based upon current flow therein.
28. An integrated circuit according to claim 27, wherein both of said plurality of first wires and said plurality of second wires contain wires having widths that differ based upon current flow therein.
29. An integrated circuit, comprising:
an area array of electrical contacts defining a plurality of contiguous rectangular regions each having a first axis of symmetry and a second axis of symmetry transverse to said first axis of symmetry; and
an electrical bus grid formed within each of said contiguous rectangular regions, said repeatable electrical bus grid comprising:
a first metal layer electrically connected to said electrical contacts;
a plurality of first wires located in said first metal layer and extending parallel to said first axis of symmetry and spaced laterally from one another;
wherein said plurality of first wires in each of said contiguous rectangular region have first widths that generally decrease in a direction toward said first axis of symmetry.
30. An integrated circuit according to claim 29, wherein said first widths decrease logarithmically to said first axis of symmetry.
31. An integrated circuit according to claim 30, further comprising a second metal layer spaced from said first metal layer and a plurality of second wires located in said second metal layer and extending parallel to said second axis of symmetry and spaced laterally from one another, said plurality of second wires being electrically connected to said plurality of first wires and having second widths that generally decrease in a direction toward said second axis of symmetry.
32. An integrated circuit according to claim 31, wherein said first widths decrease logarithmically toward said first axis of symmetry and said second widths decrease logarithmically toward said second axis of symmetry.