1. A low power, small area temperature sensor circuit comprising:
a current mirror reference circuit which produces a reference voltage,
an amplifier for reference voltage multiplying said reference voltage wherein said amplifier outputs a multiplied reference voltage,
a bank of voltage comparators wherein said multiplied reference voltage provides a minus input to said voltage comparators,
a current mirror output circuit which generates multiple voltage levels each of which are plus inputs to said voltage comparators.
2. The low power, small area temperature sensor circuit of claim 1 wherein said current mirror reference circuit is comprised of:
a first bipolar transistor connected as a diode with a base and a collector connected in common to ground,
a second bipolar transistor connected as a diode with a base and a collector connected in common to ground, wherein said second bipolar transistor has an area which is M times an area of said first bipolar transistor, where M is greater than one,
an amplifier whose minus input is connected to an emitter of said first bipolar transistor and whose plus input is connected to a first node of and input resistor whose second node is connected to an emitter a second transistor of said two bipolar transistors,
three p-channel metal oxide semiconductor field effect transistors, PMOS FETs whose sources are connected to a power supply and whose gates are connected to an output of said amplifier, wherein said common gate connection allows said three PMOS FETS to have identical current flow, wherein a first PMOS FET of said three PMOS FETS has its drain connected to said emitter of said first bipolar transistor, and a second PMOS FET of said three PMOS FETS has its drain connected to said first node of said input resistor and a third PMOS FET of said three PMOS FETS has its drain connected to a first node of a first output resistor located in an output current mirror circuit branch.
3. The low power, small area temperature sensor circuit of claim 2 wherein said reference voltage amplifier has a plus input connected to said second node of said input resistor, and said reference voltage amplifier has a minus input connected to a first node of a first reference voltage amplifier resistor, whose second node is connected to ground, wherein said reference voltage amplifier has an output which is connected to a first node of a second reference voltage amplifier resistor, whose second node is connected to said first node of said first reference voltage resistor, wherein if an amplification multiplier for said reference voltage amplifier is N and assuming said first reference voltage amplifier resistor is represented by 1, then said second reference voltage amplifier resistor would be represented by N\u22121.
4. The low power, small area temperature sensor circuit of claim 3 wherein said bank of voltage comparators is comprised of:
a first voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first node of said first output resistor, and whose output is transited and indicates a lowest absolute temperature has been detected,
a second voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first node of said second output resistor, and whose output is transited and indicates a second lowest absolute temperature has been detected,
a third voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first node of said third output resistor, and whose output is transited and indicates a third lowest absolute temperature has been detected.
5. The low power, small area temperature sensor circuit of claim 4 wherein said current mirror output circuit is comprised of said third PMOS FET of said three PMOS FETS whose drain is connected to said first node of said first output resistor, wherein said second output resistor has a second node connected to a first node of a third output resistor, wherein a second node of said third output resistor is connected to ground.
6. The low power, small area temperature sensor circuit of claim 5 wherein a voltage at said first node of said first output resistor is directly proportional to said lowest absolute temperature of a semiconductor die containing said temperature sensor circuit and wherein a voltage at said first node of said second output resistor is directly proportional to said second lowest absolute temperature of said semiconductor die containing said temperature sensor circuit, and wherein a voltage at said first node of said third output resistor is directly proportional to said third lowest absolute temperature of said semiconductor die containing said temperature sensor circuit.
7. A low power, small area temperature sensor circuit comprising:
a current mirror reference circuit which produces a reference voltage,
an amplifier for reference voltage multiplying said reference voltage wherein said amplifier outputs a multiplied reference voltage,
a pair of voltage comparators wherein said multiplied reference voltage provides a minus input to said voltage comparators,
a current mirror output circuit which generates multiple voltage levels each of which are plus inputs to said voltage comparators,
a first group of three transfer gate FETs which selectively connect different output voltage levels to a plus input of a first voltage comparator of said pair of voltage comparators, and
a second group of three transfer gate FETs which selectively connect different output voltage levels to a plus input of a second voltage comparator of said pair of voltage comparators.
8. The low power, small area temperature sensor circuit of claim 7 wherein said current mirror reference circuit is comprised of:
a first bipolar transistor connected as a diode with a base and a collector connected in common to ground,
a second bipolar transistor connected as a diode with a base and a collector connected in common to ground, wherein said second bipolar transistor has an area which is M times an area of said first bipolar transistor, where M is greater than one,
an amplifier whose minus input is connected to an emitter of said first bipolar transistor and whose plus input is connected to a first node of and input resistor whose second node is connected to an emitter a second transistor of said two bipolar transistors,
three p-channel metal oxide semiconductor field effect transistors, PMOS FETs whose sources are connected to a power supply and whose gates are connected to an output of said amplifier, wherein said common gate connection allows said three PMOS FETS to have identical current flow, wherein a first PMOS FET of said three PMOS FETS has its drain connected to said emitter of said first bipolar transistor, and a second PMOS FET of said three PMOS FETS has its drain connected to said first node of said input resistor and a third PMOS FET of said three PMOS FETS has its drain connected to a first node of a first output resistor located in an output current mirror circuit branch.
9. The low power, small area temperature sensor circuit of claim 8 wherein said reference voltage amplifier has a plus input connected to said second node of said input resistor, and said reference voltage amplifier has a minus input connected to a first node of a first reference voltage amplifier resistor, whose second node is connected to ground, wherein said reference voltage amplifier has an output which is connected to a first node of a second reference voltage amplifier resistor, whose second node is connected to said first node of said first reference voltage resistor, wherein if an amplification multiplier for said reference voltage amplifier is N and assuming said first reference voltage amplifier resistor is represented by 1, then said second reference voltage amplifier resistor would be represented by N\u22121.
10. The low power, small area temperature sensor circuit of claim 9 wherein said pair of voltage comparators is comprised of:
a first voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first group of transfer gate FETs, which connect said first node of said first output resistor or said first node of said second output resistor or said first node of said third output resistor, depending on said state control mode, and whose output is latched and whose level and transitions are used in combination with said state control mode to determine an absolute temperature level,
a second voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said second group of transfer gate FETs, which connect said first node of said first output resistor or said first node of said second output resistor or said first node of said third output resistor, depending on said state control mode, and whose output is latched and whose level and transitions are used in combination with said state control mode to determine an absolute temperature level.
11. The low power, small area temperature sensor circuit of claim 10 wherein said current mirror output circuit is comprised of said third PMOS FET of said three PMOS FETS whose drain is connected to said first node of said first output resistor, wherein said second output resistor has a second node connected to a first node of a third output resistor, wherein a second node of said third output resistor is connected to ground.
12. The low power, small area temperature sensor circuit of claim 11 wherein a voltage at said first node of said first output resistor is directly proportional to said lowest absolute temperature of a semiconductor die containing said temperature sensor circuit and wherein a voltage at said first node of said second output resistor is directly proportional to said second lowest absolute temperature of said semiconductor die containing said temperature sensor circuit, and wherein a voltage at said first node of said third output resistor is directly proportional to said third lowest absolute temperature of said semiconductor die containing said temperature sensor circuit.
13. The low power, small area temperature sensor circuit of claim 12, wherein said first group of three transfer gate FETs have their drains connected in common to a plus input of said first voltage comparator of said pair of voltage comparators, wherein said said first group of three transfer gate FETs have their sources connected to said first node of said first output resistor, to said first node of said second output resistor, and to said first node of said third output resistor respectively, and wherein said first group of three transfer gate FETs have their gates connected to control signals derived from said state control modes.
14. The low power, small area temperature sensor circuit of claim 13, wherein a number of absolute temperatures to be detected can be added by adding one said output resistor and one said transfer gate FET for each said absolute temperature to be detected.
15. The low power, small area temperature sensor circuit of claim 14, wherein a number of said state control modes is equal to said number of temperatures to be detected plus one.
16. The low power, small area temperature sensor circuit of claim 15, wherein said pair of voltage comparators are duplicated as said number of temperatures to be detected is increased beyond a circuit loading limitation of said transfer gate FETs.
17. A method of sensing integrated circuit temperatures using low power and small area comprising the steps of:
producing a reference voltage using a current mirror reference circuit,
multiplying said reference voltage using an amplifier,
providing a bank of voltage comparators wherein said multiplied reference voltage provides a minus input to said voltage comparators, and
providing a current mirror output circuit which generates multiple voltage levels each of which are plus inputs to said voltage comparators.
18. The method of sensing integrated circuit temperatures using low power and small area of claim 17 wherein said current mirror reference circuit is comprised of:
a first bipolar transistor connected as a diode with a base and a collector connected in common to ground,
a second bipolar transistor connected as a diode with a base and a collector connected in common to ground, wherein said second bipolar transistor has an area which is M times an area of said first bipolar transistor, where M is greater than one,
an amplifier whose minus input is connected to an emitter of said first bipolar transistor and whose plus input is connected to a first node of and input resistor whose second node is connected to an emitter a second transistor of said two bipolar transistors,
three p-channel metal oxide semiconductor field effect transistors, PMOS FETs whose sources are connected to a power supply and whose gates are connected to an output of said amplifier, wherein said common gate connection allows said three PMOS FETS to have identical current flow, wherein a first PMOS FET of said three PMOS FETS has its drain connected to said emitter of said first bipolar transistor, and a second PMOS FET of said three PMOS FETS has its drain connected to said first node of said input resistor and a third PMOS FET of said three PMOS FETS has its drain connected to a first node of a first output resistor located in an output current mirror circuit branch.
19. The method of sensing integrated circuit temperatures using low power and small area of claim 18 wherein said reference voltage amplifier has a plus input connected to said second node of said input resistor, and said reference voltage amplifier has a minus input connected to a first node of a first reference voltage amplifier resistor, whose second node is connected to ground, wherein said reference voltage amplifier has an output which is connected to a first node of a second reference voltage amplifier resistor, whose second node is connected to said first node of said first reference voltage resistor, wherein if an amplification multiplier for said reference voltage amplifier is N and assuming said first reference voltage amplifier resistor is represented by 1, then said second reference voltage amplifier resistor would be represented by N\u22121.
20. The method of sensing integrated circuit temperatures using low power and small area of claim 19 wherein said bank of voltage comparators is comprised of:
a first voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first node of said first output resistor, and whose output is transited and indicates a lowest absolute temperature has been detected,
a second voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first node of said second output resistor, and whose output is transited and indicates a second lowest absolute temperature has been detected,
a third voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first node of said third output resistor, and whose output is transited and indicates a third lowest absolute temperature has been detected.
21. The method of sensing integrated circuit temperatures using low power and small area of claim 20 wherein said current mirror output circuit is comprised of said third PMOS FET of said three PMOS FETS whose drain is connected to said first node of said first output resistor, wherein said second output resistor has a second node connected to a first node of a third output resistor, wherein a second node of said third output resistor is connected to ground.
22. The method of sensing integrated circuit temperatures using low power and small area of claim 21 wherein a voltage at said first node of said first output resistor is directly proportional to said lowest absolute temperature of a semiconductor die containing said temperature sensor circuit and wherein a voltage at said first node of said second output resistor is directly proportional to said second lowest absolute temperature of said semiconductor die containing said temperature sensor circuit, and wherein a voltage at said first node of said third output resistor is directly proportional to said third lowest absolute temperature of said semiconductor die containing said temperature sensor circuit.
23. A method of sensing integrated circuit temperatures using low power and small area comprising the steps of:
producing a reference voltage using a current mirror reference circuit,
multiplying said reference voltage using an amplifier,
providing a pair of voltage comparators wherein said multiplied reference voltage provides a minus input to said voltage comparators,
providing a current mirror output circuit which generates multiple voltage levels each of which are plus inputs to said voltage comparators,
providing a first group of three transfer gate FETs which selectively connect different output voltage levels to a plus input of a first voltage comparator of said pair of voltage comparators, and
providing a second group of three transfer gate FETs which selectively connect different output voltage levels to a plus input of a second voltage comparator of said pair of voltage comparators.
24. The method of sensing integrated circuit temperatures using low power and small area of claim 23 wherein said current mirror reference circuit is comprised of:
a first bipolar transistor connected as a diode with a base and a collector connected in common to ground,
a second bipolar transistor connected as a diode with a base and a collector connected in common to ground, wherein said second bipolar transistor has an area which is M times an area of said first bipolar transistor, where M is greater than one,
an amplifier whose minus input is connected to an emitter of said first bipolar transistor and whose plus input is connected to a first node of and input resistor whose second node is connected to an emitter a second transistor of said two bipolar transistors,
three p-channel metal oxide semiconductor field effect transistors, PMOS FETs whose sources are connected to a power supply and whose gates are connected to an output of said amplifier, wherein said common gate connection allows said three PMOS FETS to have identical current flow, wherein a first PMOS FET of said three PMOS FETS has its drain connected to said emitter of said first bipolar transistor, and a second PMOS FET of said three PMOS FETS has its drain connected to said first node of said input resistor and a third PMOS FET of said three PMOS FETS has its drain connected to a first node of a first output resistor located in an output current mirror circuit branch.
25. The method of sensing integrated circuit temperatures using low power and small area of claim 24 wherein said reference voltage amplifier has a plus input connected to said second node of said input resistor, and said reference voltage amplifier has a minus input connected to a first node of a first reference voltage amplifier resistor, whose second node is connected to ground, wherein said reference voltage amplifier has an output which is connected to a first node of a second reference voltage amplifier resistor, whose second node is connected to said first node of said first reference voltage resistor, wherein if an amplification multiplier for said reference voltage amplifier is N and assuming said first reference voltage amplifier resistor is represented by 1, then said second reference voltage amplifier resistor would be represented by N\u22121.
26. The method of sensing integrated circuit temperatures using low power and small area of claim 25 wherein said pair of voltage comparators is comprised of:
a first voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said first group of transfer gate FETs, which connect said first node of said first output resistor or said first node of said second output resistor or said first node of said third output resistor, depending on said state control mode, and whose output is latched and whose level and transitions are used in combination with said state control mode to determine an absolute temperature level,
a second voltage comparator whose minus input is said output of said reference voltage amplifier and whose plus input is from said second group of transfer gate FETs, which connect said first node of said first output resistor or said first node of said second output resistor or said first node of said third output resistor, depending on said state control mode, and whose output is latched and whose level and transitions are used in combination with said state control mode to determine an absolute temperature level.
27. The method of sensing integrated circuit temperatures using low power and small area of claim 26 wherein said current mirror output circuit is comprised of said third PMOS FET of said three PMOS FETS whose drain is connected to said first node of said first output resistor, wherein said second output resistor has a second node connected to a first node of a third output resistor, wherein a second node of said third output resistor is connected to ground.
28. The method of sensing integrated circuit temperatures using low power and small area of claim 27 wherein a voltage at said first node of said first output resistor is directly proportional to said lowest absolute temperature of a semiconductor die containing said temperature sensor circuit and wherein a voltage at said first node of said second output resistor is directly proportional to said second lowest absolute temperature of said semiconductor die containing said temperature sensor circuit, and wherein a voltage at said first node of said third output resistor is directly proportional to said third lowest absolute temperature of said semiconductor die containing said temperature sensor circuit.
29. The method of sensing integrated circuit temperatures using low power and small area of claim 28, wherein said first group of three transfer gate FETs have their drains connected in common to a plus input of said first voltage comparator of said pair of voltage comparators, wherein said first group of three transfer gate FETs have their sources connected to said first node of said first output resistor, to said first node of said second output resistor, and to said first node of said third output resistor respectively, and wherein said first group of three transfer gate FETs have their gates connected to control signals derived from said state control modes.
30. The method of sensing integrated circuit temperatures using low power and small area of claim 29, wherein a number of absolute temperatures to be detected can be added by adding one said output resistor and one said transfer gate FET for each said absolute temperature to be detected.
31. The method of sensing integrated circuit temperatures using low power and small area of claim 30, wherein a number of said state control modes is equal to said number of temperatures to be detected plus one.
32. The method of sensing integrated circuit temperatures using low power and small area of claim 31, wherein said pair of voltage comparators are duplicated as said number of temperatures to be detected is increased beyond a circuit loading limitation of said transfer gate FETs.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An in-wheel motor system having a hollow direct drive motor which is provided in a wheel and whose stator side is supported to a part around the wheel of a vehicle by elastic bodies andor an attenuation mechanism, wherein
a motor rotor and a wheel or a hub are interconnected by a coupling mechanism which comprises a wheel-side plate connected to the wheel or hub, a motor-side plate connected to the rotating side case of the motor, an intermediate plate interposed between these two plates, and first and second slide members for interconnecting between the wheel-side plate and the intermediate plate and between the intermediate plate and the motor-side plate, each having roller members whose moving directions are limited by guide portions, and arranged in such a manner that their moving directions are orthogonal to each other.
2. The in-wheel motor system according to claim 1, wherein contact portions which extend in the moving directions of the roller members and are brought into contact with the side faces of the roller members are provided on the intermediate plate to limit the moving directions of the roller members.
3. The in-wheel motor system according to claim 1 or 2, comprising an elastic annular dust boot for storing the first and second slide members.
4. An in-wheel motor system having a hollow direct drive motor which is provided in a wheel and whose stator side is supported to a part around the wheel of a vehicle by elastic bodies andor an attenuation mechanism, wherein
a motor rotor and a wheel or a hub are interconnected by a coupling mechanism which comprises a wheel-side plate connected to the wheel or hub, a motor-side plate connected to the rotating side case of the motor, an intermediate plate interposed between these two plates, and first and second slide members for interconnecting between the wheel-side plate and the intermediate plate and between the intermediate plate and the motor-side plate, each consisting of linear bearings and a rod, and arranged in such a manner that their moving directions are orthogonal to each other.
5. The in-wheel motor system according to claim 4, comprising an elastic annular dust boot for storing the first and second slide members.
6. An in-wheel motor system having a hollow direct drive motor which is provided in a wheel and whose stator side is supported to a part around the wheel of a vehicle by elastic bodies andor an attenuation mechanism and a coupling member having a slide mechanism for connecting the rotor of the motor to the wheel or hub, wherein
an elastic annular dust boot for storing the slide mechanism is provided.