1. A processing unit, comprising:
an input buffer to store data received by the processing unit;
a memory, coupled to the input buffer;
an arithmetic logic unit coupled to the input buffer and to the memory, the arithmetic logic to perform operations on operands provided by the input buffer and the memory;
an output buffer coupled to the arithmetic logic unit and the memory to store data to transfer from the processing unit; and
control logic having access to a control store of program instructions, the control logic to process instructions including:
an instruction to transfer data from the input buffer to the memory;
an instruction to cause the arithmetic logic unit to perform an operation on operands provided by both the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.
2. The processing unit of claim 1, further comprising input buffer logic to store data received by the processing unit at a location in the input buffer based on the order in which the data arrived at the input buffer; and
further comprising output buffer logic to store data to transfer from the processing unit at a location in the at least one output buffer based on the order in which the data arrived at the at least one output buffer.
3. The processing unit of claim 1, further comprising the program instruction control store; and
wherein the input buffer receives program instructions; and
wherein the processing unit transfers the program instructions received by the input buffer to the program instruction control store.
4. The processing unit of claim 1, wherein the instructions comprise an instruction to set a scale of operand size.
5. The processing unit of claim 4, wherein the instruction to perform an operation on operands comprises an instruction to specify a multiple of the scale.
6. The processing unit of claim 1, wherein the memory comprises a memory divided into multiple banks;
wherein each of the banks is coupled to the arithmetic logic unit;
wherein the instruction to perform an operation on operands comprises an instruction capable of specifying operands provided by different ones of the multiple banks.
7. The processing unit of claim 1, further comprising logic to identify to the control logic detection of a bit pattern output by the arithmetic logic unit.
8. A system, comprising:
an Ethernet MAC (media access controller);
a processor coupled to the Ethernet MAC, the processor comprising:
multiple processor cores; and
multiple processing units, each of the multiple processing units comprising:
an input buffer to store data received by the processing unit;
a memory, coupled to the input buffer;
an arithmetic logic unit coupled to the input buffer and to the memory, the arithmetic logic to perform operations on operands provided by the input buffer and the memory;
an output buffer coupled to the arithmetic logic unit and the memory to store data to transfer from the processing unit; and
control logic having access to a control store of program instructions, the control logic to process instructions including:
an instruction to transfer data from the input buffer to the memory;
an instruction cause the arithmetic logic unit to perform an operation on operands provided by both the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.
9. The system of claim 8, further comprising input buffer logic to store data received by the processing unit at a location in the input buffer based on the order in which the data arrived at the input buffer; and
further comprising output buffer logic to store data to transfer from the processing unit at a location in the at least one output buffer based on the order in which the data arrived at the at least one output buffer.
10. The system of claim 8, further comprising the program instruction control store; and
wherein the input buffer receives program instructions; and
wherein the processing unit transfers the program instructions received by the input buffer to the program instruction control store.
11. The system of claim 8, wherein the instructions comprise an instruction to set a scale of operand size.
12. The system of claim 11, wherein the instruction to perform an operation on operands comprises an instruction to specify a multiple of the scale.
13. The system of claim 8, wherein the memory comprises a memory divided into multiple banks;
wherein each of the banks is coupled to the arithmetic logic unit;
wherein the instruction to perform an operation on operands comprises an instruction capable of specifying operands provided by different ones of the multiple banks.
14. The system of claim 8, further comprising dedicated logic to identify to the control logic identification of a bit pattern output by the arithmetic logic unit.
15. A computer program, disposed on a computer readable medium, the program comprising instructions to cause control logic of a processing unit to:
transfer data from a input buffer to store data received by the processing unit to a memory coupled to the input buffer;
cause an arithmetic logic unit coupled to the input buffer and the memory to perform an operation on operands provided by both the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and an output buffer.
16. The program of claim 15, wherein the instructions cause the control logic of the processing unit to set a scale of operand size.
17. The program of claim 15, wherein the instructions cause the control logic of the processing unit to perform an operation by the arithmetic logic unit on operands provided by different respective banks of the memory.
18. The program of claim 15, wherein the instructions cause the control logic of the processing unit to respond to a signal provided to the control logic identifying detection of a bit pattern output by the arithmetic logic unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-6. (canceled)
7. A system for generating one or more test cases for a service of a server system comprising:
at least one processor configured to:
analyze metadata associated with the service to generate a schema definition for inputs and outputs of the service;
generate a description of the service in an application description language that refers to the schema definition; and
process the generated description of the service to produce the one or more test cases.
8. The system of claim 7, wherein the service includes an Extract, Transform, Load (ETL) job.
9. The system of claim 7, wherein the schema definition includes an Extensible Markup Language Schema Definition (XSD) grammar, and the application description language includes Web Application Descriptor Language (WADL).
10. The system of claim 7, wherein the one or more test cases include at least one of a test script and a Java application.
11. The system of claim 7, wherein the service is of a third party server system, and the one or more test cases are produced by one or more clients of the service.
12. The system of claim 7, wherein the one or more test cases test at least one of an input parameter and an output of a process of the service for compliance with a data restriction, wherein the data restriction indicates acceptable data for the input parameter and the output.
13. A computer program product for generating one or more test cases for a service of a server system comprising:
a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising computer readable program code configured to:
analyze metadata associated with the service to generate a schema definition for inputs and outputs of the service;
generate a description of the service in an application description language that refers to the schema definition; and
process the generated description of the service to produce the one or more test cases.
14. The computer program product of claim 13, wherein the service includes an Extract, Transform, Load (ETL) job.
15. The computer program product of claim 13, wherein the schema definition includes an Extensible Markup Language Schema Definition (XSD) grammar, and the application description language includes Web Application Descriptor Language (WADL).
16. The computer program product of claim 13, wherein the one or more test cases include at least one of a test script and a Java application.
17. The computer program product of claim 13, wherein the service is of a third party server system, and the one or more test cases are produced by one or more clients of the service.
18. The computer program product of claim 13, wherein the one or more test cases test at least one of an input parameter and an output of a process of the service for compliance with a data restriction, wherein the data restriction indicates acceptable data for the input parameter and the output.