1. An optical probe comprising a fiber array and a spacing sensor positioned above a plurality of optical structures disposed on an integrated substrate, wherein the spacing sensor measures a distance between the optical probe and the substrate, wherein the plurality of optical structures comprises an optical alignment loop disposed on the integrated substrate, wherein the fiber array of the optical probe is aligned with the alignment loop.
2. An optical probe according to claim 1, wherein the spacing sensor comprises a capacitance sensor.
3. An optical probe according to claim 1, wherein the optical probe comprises a light source and an optical detector.
4. An optical probe according to claim 1, wherein the fiber array comprises a plurality of optical fibers, and at least one of the optical fibers is selected from a group comprising:
a single mode fiber,
a polarization maintaining fiber,
a multi-mode fiber and
a lensed fiber.
5. An optical probe according to claim 1, and further comprising:
an optical probe positioner, where the optical probe positioner controls the position of the optical probe with respect to the integrated substrate,
a substrate positioner, where the substrate positioner controls the position of the substrate with respect to the optical probe,
and
a control system to control the optical probe positioner and the substrate positioner, where the control system is coupled to the spacing sensor and the control system controls the spacing between the optical probe and the integrated substrate.
6. An optical probe according to claim 5, wherein the control system maintains a selected spacing between the optical probe and the substrate.
7. An optical probe according to claim 5, wherein the control system performs a procedure to increase the spacing between the optical probe and the substrate, where the procedure to increase the spacing is performed prior to the lateral movement of the substrate with respect to the optical probe.
8. An optical probe according to claim 1, wherein the integrated substrate is selected from a group comprising: a wafer, a die and an integrated circuit.
9. An optical probe according to claim 1, wherein the optical loop comprises a plurality of optical inputoutput (IO) couplers separated from each other to define a line parallel to an array of optical ports disposed on the integrated substrate, wherein each of the plurality of optical IO couplers are optically aligned to a corresponding fiber in the fiber array of the optical probe.
10. An optical probe according to claim 9, wherein the alignment loop further comprises a waveguide coupled to each of the plurality of optical IO couplers, wherein one fiber of the fiber array sends a probe beam to the alignment loop and another fiber of the fiber array receives light output from the alignment loop.
11. An optical probe according to claim 1, wherein the alignment loop comprises a plurality of optical ports within an array of ports disposed on the integrated substrate, wherein each of the plurality of optical ports are optically aligned to a corresponding fiber in the fiber array of the optical probe.
12. An optical probe according to claim 1, wherein the alignment loop comprises a plurality of reflective or diffractive alignment structures disposed on the integrated substrate, wherein each of the plurality of alignment structures are optically aligned to a corresponding fiber in the fiber array of the optical probe.
13. An optical probe according to claim 1, wherein the fiber array of the optical probe is aligned to the alignment loop in three dimensions, X, Y, and Z, wherein Z is the distance between the optical probe and the substrate.
14. An optical probe according to claim 13, wherein the plurality of optical structures are passive, wherein the plurality of passive optical structures serve to measure a relative lateral (XY) position of the optical probe.
15. An optical probe according to claim 13, wherein the spacing sensor measures a relative vertical (Z) position.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A magnetic random access memory comprising:
a magneto resistive element;
a first insulating layer which covers side surfaces of the magneto resistive element;
a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element;
a write line which fills the first groove and is connected with the magneto resistive element; and
a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.
2. The magnetic random access memory according to claim 1, wherein the second insulating layer has a second groove around a memory cell array section in which the magneto resistive element is arranged, an electroconductive layer is filled in the second groove, and the third insulating layer exists only in the memory cell array section.
3. The magnetic random access memory according to claim 1, wherein the third insulating layer has a function to prevent molecules including hydrogen, oxygen and water or atoms constituting them from permeating.
4. The magnetic random access memory according to claim 3, wherein the third insulating layer is one of SiN, AlO3 and Al2O3.
5. The magnetic random access memory according to claim 1, further comprising a cap layer which is arranged between the magneto resistive element and the write line and has a thickness of 5 to 100 nm.
6. The magnetic random access memory according to claim 1, wherein a thickness of the second insulating layer is 300 to 500 nm, and a thickness of the third insulating layer is 20 to 100 nm.
7. The magnetic random access memory according to claim 1, wherein the write line is constituted of an electroconductive layer and yoke layers which cover at least all or part of a surface of the electroconductive layer except a bottom surface thereof.
8. The magnetic random access memory according to claim 7, wherein the electroconductive layer is constituted of copper.
9. The magnetic random access memory according to claim 1, wherein an easy axis of the magneto resistive element is directed in a direction vertical to a direction along which the write line extends.
10. The magnetic random access memory according to claim 4, wherein a free layer of the magneto resistive element is in contact with the cap layer.
11. The magnetic random access memory according to claim 4, wherein a pin layer of the magneto resistive element is in contact with the cap layer.
12. The magnetic random access memory according to claim 1, wherein the magneto resistive element is connected with a MOS transistor arranged directly below the magneto resistive element.
13. The magnetic random access memory according to claim 1, wherein another write line orthogonal to the write line is arranged below the magneto resistive element.
14. A manufacturing method of a magnetic random access memory comprising:
forming a cap layer on a magneto resistive element;
forming a first insulating layer which covers the magneto resistive element and the cap layer and whose top surface exists at the level of a top surface of the cap layer;
forming a second insulating layer on the first insulating layer;
removing the second insulating layer existing around a memory cell array section in which the magneto resistive element is arranged;
forming a third insulating layer on the first and second insulating layers;
forming a first groove above the cap layer and forming a second groove around the memory cell array section by etching the third insulating layer;
etching the second insulating layer exposed on a bottom portion of the first groove; and
filling an electroconductive layer in the first and second grooves.
15. The manufacturing method according to claim 14, wherein a top surface of the first insulating layer is caused to be at the level with a top surface of the cap layer by a CMP method.
16. The manufacturing method according to claim 14, wherein the electroconductive layer is filled in the first and second grooves at the same time.
17. The manufacturing method according to claim 14, further comprising forming a first yoke layer on side walls of the first groove before filling the electroconductive layer in the first and second grooves.
18. The manufacturing method according to claim 17, further comprising forming a second yoke layer on the electroconductive layer after filling the electroconductive layer in the first and second grooves.
19. The manufacturing method according to claim 14, wherein the first and third insulating layers are silicon oxide, and the second insulating layer is one of SiN, AlO3 and Al2O3.
20. The manufacturing method according to claim 14, wherein the cap layer is formed so as to have a thickness of 5 to 100 nm.