1. A paper identification counter comprising:
a counter body;
a hopper disposed at a top portion of the counter body;
a stacker disposed at a front portion of the counter body;
a conveyance passage formed in the counter body so as to extend from the hopper to the stacker;
a feed mechanism for feeding papers stacked on a bottom of the conveyance passage; and
a delivery mechanism for delivering the papers from the feed mechanism to the conveyance passage;
said feed mechanism and said delivery mechanism having a feed roller and a delivery roller, respectively, which are rotationally driven in synchronism with each other, said feed roller and said delivery roller each being formed, at a portion in a circumferential direction thereof, a friction member for providing a paper feed frictional force, said feed roller and said delivery roller being each provided with a balancer weight at a location diametrically opposing said friction member.
2. A paper identification counter according to claim 1, wherein said delivery mechanism includes a stop member coming into press contact with the delivery roller, the stop member preventing papers from being fed in an overlapped manner.
3. A paper identification counter according to claim 1, further comprising a pocket disposed above the stacker and adapted to store therein papers rejected from the conveyance passage, said pocket including a pocket bearer and a support member covering the pocket bearer from a front side thereof.
4. A paper identification counter according to claim 3, wherein said pocket includes a pocket bearer disposed at a free end of a guide arm of a reject conveyance passage opening mechanism, a forward extending pocket arm securely fastened to the counter body and a support member interposed between the free end of said pocket arm and the fore-end of said pocket bearer, said support member being supported by one of the free end of the pocket arm and the fore-end of the pocket bearer and being releasably fixed to another one thereof.
5. A paper identification counter according to claim 3, wherein said pocket is opened at both sides thereof, a front side portion of the pocket being covered with a pair of side members which are supported by one of said free end of the pocket arm and said fore-end of the pocket bearer, said pair of side members being releasably fixed to another one thereof by a one-touch fastener.
6. A paper identification counter according to claim 5, wherein said one-touch fastener includes a magnet.
7. A paper identification counter according to claim 3, wherein said support member is provided with a shock absorbing resilient member adhering an inside portion of the pocket and said support bearer is notched centrally at the front portion thereof so as to form a retrieval opening.
8. A paper identification counter according to claim 7, wherein said resilient member includes a sponge.
9. A paper identification counter according to claim 3, wherein said conveyance passage includes a rectilinear conveyance passage descending from the hopper through the delivery mechanism along the back side of the counter body, said rectilinear conveyance passage including a paper identification unit provided with a line sensor, said line sensor being a light transmission type detector including a plurality of light emission elements which are arrayed in the width direction of the conveyance passage and including a plurality of light reception elements which confront the light emission elements in a one-to-one corresponding manner, and said paper identification counter including a scanning processing circuit arranged to serially scan in line a train of said light reception elements of said line sensor, and an arithmetic CPU arranged to process serial scanning data from the scanning processing circuits.
10. A paper identification counter according to claim 9, wherein said scanning processing circuit includes a sensor scanning circuit for serially scanning the train of the light reception elements of the line sensor in response to a drive signal from the control CPU and to an encoder drive signal from an encoder detecting the rotational speed of the delivery roller of the delivery mechanism, a signal processing circuit for processing test data signals as a result of serial scanning of the train of the light reception elements, and an AD converter for converting an analog signal to a digital signal so as to input a test data digital signal from said AD converter to said arithmetic CPU.
11. A paper identification counter according to claim 9, wherein said control CPU and said arithmetic CPU are mounted on a circuit board accommodated in a side space inside the counter body, said control CPU performing a control of a delivery drive motor, a conveyance drive motor, a brake for stopping said delivery drive motor and various sensors, said arithmetic CPU being an arithmetic only processor processing a scanning data from the line sensor.
12. A paper identification counter according to claim 9, wherein said control CPU issues startstop and brake signals for a delivery drive motor and a conveyance drive motor to a motor driver, said control CPU providing a rotation control of the drive motors by way of an autonomous rotation control circuit which receives a reference clock signal from the control CPU and a signal from an encoder detecting the rotational speed of the delivery drive motor and the conveyance drive motor.
13. A paper identification counter according to claim 9, wherein said control CPU includes a bus emulator circuit intervening between said control CPU and a display panel such as an LCD, said bus emulator circuit achieving matching with an interface of said display panel to partially share processing to be effected by the control CPU.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A flash memory device comprising:
a control logic circuit to generate cache input control signals, cache output control signals and chip enable signals having a plurality of bit signals, wherein:
the cache input control signals correspond to the bit signals,
each cache input control signal is generated when a corresponding bit signal changes from a high level to a low level,
the control logic circuit receives addresses when the bit signals are at a low level,
the cache input control signals are generated in sequence during a program operation or are simultaneously generated during a read operation, and
the cache output control signals are simultaneously generated in the program operation or are generated in sequence in the read operation;
a plurality of planes each including a plurality of memory cell blocks, wherein:
the number of planes corresponds to the number of bit signals of each chip enable signal, and
in the program operation, data is simultaneously programmed in each of the plurality of planes based on the corresponding bit signals;
a plurality of page buffers, each page buffer arranged in correspondence with one of the planes, each page buffer simultaneously latching an input data bit to be output to its corresponding plane or simultaneously latching an output data bit to be received from the corresponding plane; and
a plurality of cache buffers, each cache buffer being arranged in correspondence with one of the page buffers and the corresponding plane, wherein:
in the read operation, the data programmed in the plurality of planes is simultaneously output to the plurality of cache buffers based on the corresponding bit signals,
the cache buffers store in sequence the input data bits in response to the cache input control signals in the program operation or simultaneously store the latched output data bits in response to the cache input control signals in the read operation, and
the cache buffers simultaneously transfer the stored data bits to the corresponding page buffers in response to the cache output control signals in the program operation or transfer the stored data bits in sequence to an external device in response to the cache output control signals in the read operation.
2. The flash memory device as set forth in claim 1, wherein the control logic circuit generates one among a program command, a read command, and an erase command in response to the command signal, and generates row and column address signals in response to an external address signal.
3. The flash memory device as set forth in claim 1, wherein the number of the bit signals for each chip enable signal is identical to the number of the planes.
4. The flash memory device as set forth in claim 2, further comprising:
a high voltage generator generating bias voltages in response to one among the program voltage, the read command, and the erase command;
an X-decoder selecting one of the memory cell blocks included in each of the planes on basis of the row address signal and supplying the bias voltages to the selected memory cell block; and
a Y-decoder decoding the column address signal and applying the column address signal to the page buffers,
wherein the page buffers select bitlines of corresponding planes partially or entirely in response to the column decoding signal, and output the input data bits to the selected bitlines or latch the output data bits received from the selected bitlines.
5. The flash memory device as set forth in claim 2, wherein the control logic circuit generates the program command when the command signal contains a page program setup code, and disables a readybusy signal for a first predetermined time when receiving the command signal containing a confirmation code after generating the program command.
6. The flash memory device as set forth in claim 5, wherein the control logic circuit, after generating the program command, enables the cache input control signals one by one in sequence for a second predetermined time when the bit signals are changed into a predetermined logic value one by one in sequence for the second predetermined time, and enables the cache output control signals at the same time while the readybusy signal is being disabled when the bit signals are changed into the predetermined logic value at the same time for the first predetermined time, and
wherein the cache buffers store the input data bits one by one in sequence when the cache input control signals are enabled one by one in sequence, and outputs the stored data bits to the page buffers at the same time when the cache output control signals are enabled at the same time.
7. The flash memory device as set forth in claim 6, wherein after storing the input data bits stored in the last one of the cache buffers, the bit signals are changed to the predetermined logic value at the same time for the first predetermined time.
8. The flash memory device as set forth in claim 2, wherein the control logic circuit generates the read command when the command signal contains a read code, and disables a readybusy signal for a first predetermined time when the external address signal is received after generating the read command.
9. The flash memory device as set forth in claim 8, wherein the control logic circuit, after generating the read command, enables the cache input control signals at the same time while the readybusy signal is being disabled, and enables the cache output control signals one by one in sequence for a second predetermined time when the bit signals are changed into a predetermined logic value one by one in sequence for the second predetermined time, and
wherein the cache buffers store the latched output data bits received from the page buffers when the cache input control signals are enabled at the same time, and output the stored data bits to the external device one by one in sequence when the cache output control signals are enabled one by one in sequence.
10. The flash memory device as set forth in claim 9, wherein the bit signals are changed into the predetermined logic value when the control logic circuit receives the command signal, being maintained in the predetermined logic value when the readybusy signal is being disabled.
11. The flash memory device as set forth in claim 9, wherein the bit signals are changed into the predetermined logic value one by one in sequence for the second predetermined time after the latched output data bits are sequentially stored in the cache buffers.
12. A method of controlling a program operation of a multi-plane type flash memory device, the method comprising:
generating a program command in response to a command signal;
receiving addresses when a plurality of chip enable signals having a plurality of bit signals change to a low level;
storing input data bits into cache buffers arranged in correspondence with a plurality of planes, wherein:
the number of planes corresponds to the number of bit signals,
each plane comprises a plurality of memory blocks, and
the cache buffers operate in sequence in response to cache input control signals which are enabled in sequence in the program operation;
generating bias voltages for the program operation in response to the program command;
selecting one of the memory cell blocks of each of the planes according to row and column address signals which are generated by the addresses;
applying the bias voltages to the selected memory cell blocks;
simultaneously outputting data bits stored in the cache buffers to page buffers of the planes in response to cache output control signals which are simultaneously enabled in the program operation; and
simultaneously programming the data bits from the page buffers to the selected memory cell blocks based on the corresponding bit signals.
13. The method as set forth in claim 12, wherein the storing-input-data-bits step comprises:
enabling the cache input control signals one by one in sequence for a predetermined time in response to the chip enable signals;
storing the input data bits in a corresponding one of the cache buffers in response to one of the cache input control signals; and
repeating the enabling-cache-input-control-signals step and storing-the-input-data-bits step until the input data bits are stored up to the last one of the cache buffers.
14. The method as set forth in claim 13, wherein the enabling step comprises:
changing the bit signals of the chip enable signals into a predetermined logic value one by one in sequence for the predetermined time after generation of the program command.
15. The method as set forth in claim 13, wherein the storing-input-data-bits step further comprises:
changing the bit signals of the chip enable signals into a predetermined logic value simultaneously for a predetermined time after the input data bits are stored up to the last one of the cache buffers.
16. The method as set forth in claim 12, wherein the outputting step comprises:
enabling cache output control signals simultaneously, when the bit signals of the chip enable signals are changed into a predetermined logic value simultaneously for a first predetermined time and for a second predetermined time after generation of the program command;
outputting data bits stored in the cache buffers to the page buffers that are each coupled to at least one of the cache buffers and arranged in correspondence with the plurality of planes, in response to the cache output control signals; and
latching the stored data bits in the page buffers and outputting the latched data bits each to the plurality of planes.
17. A method of controlling a read operation of a multi-plane type flash memory device, the method comprising:
generating a read command in response to a command signal;
receiving addresses when a plurality of chip enable signals having a plurality of bit signals change to a low level;
generating bias voltages for the read operation in response to the read command;
selecting one memory cell block of a plurality of memory cell blocks from each of a plurality of planes, wherein:
the number of planes corresponding to the number of bit signals, and
each of the memory cell blocks are selected according to row and column address signals which are generated by the addresses;
applying the bias voltages to the selected memory cell blocks;
simultaneously outputting data bits programmed in the selected memory cell blocks of the planes based on the corresponding bit signals;
storing the output data bits of the planes simultaneously in cache buffers arranged in correspondence with the planes in response to cache input control signals which are simultaneously enabled during the read operation; and
outputting the data bits stored in the cache buffers to an external device one by one in sequence in response to cache output control signals which are enabled in sequence during the read operation.
18. The method as set forth in claim 17, wherein the storing step comprises:
latching the output data bits in page buffers arranged in correspondence with the planes;
enabling cache input control signals at the same time when a readybusy signal is disabled after generation of the read command; and
storing the latched data bits simultaneously in the cache buffers coupled to the page buffers in response to the cache input control signals.
19. The method as set forth in claim 18, wherein the enabling step comprises:
changing the bit signals of the chip enable signal simultaneously into a predetermined logic value when the read command is generated and maintaining the bit signals at the predetermined logic value while the readybusy signal is being disabled.
20. The method as set forth in claim 17, wherein the outputting step comprises:
enabling the cache output control signals one by one in sequence for a predetermined time in response to the bit signals of a chip enable signal;
outputting the data bit stored in a corresponding one of the cache buffers, to the external device in response to an enabled one of the cache output control signals; and
repeating the enabling-cache-output-control-signals step and outputting step until the data bit stored in the last one of the cache buffers is output to the external device.
21. The method as set forth in claim 20, wherein the enabling step comprises:
changing the bit signals of the chip enable signal into a predetermined logic value one by one in sequence for the predetermined time after the output data bits are simultaneously stored in the cache buffers.