1. A method for calculating a branch target address comprising the steps of:
fetching a branch instruction from a memory, wherein said branch instruction stores an offset of a target address comprising n bits;
calculating n1 least significant bits of said target address of said branch instruction; and
replacing n1 least significant bits of said offset of said target address with said n1 least significant bits of said target address of said branch instruction.
2. The method as recited in claim 1 further comprises the step of:
appending a carry bit to said branch instruction thereby increasing a length of said branch instruction by one bit.
3. The method as recited in claim 2 further comprising the steps of:
calculating a set of upper order bit value combinations of an address of said branch instruction;
storing said branch instruction storing said n1 least significant bits of said target address in a cache;
retrieving said branch instruction storing said n1 least significant bits of said target address from said cache; and
selecting a one of said set of upper order bit value combinations of said address of said branch instruction.
4. The method as recited in claim 3 further comprising the step of:
appending said selected one of said set of upper order bit value combinations of said address of said branch instruction with said n1 least significant bits of said target address to calculate said target address of said branch instruction.
5. The method as recited in claim 1, wherein said step of calculating n1 least significant bits of said target address of said branch instruction comprises the step of:
adding a value stored in said n1 least significant bits of said offset of said target address stored in said branch instruction with a value stored in said n1 least significant bits of said address of said branch instruction.
6. The method as recited in claim 3, wherein said set of upper order bit value combinations of said address of said branch instruction comprises one or more of the following: a value in said upper order bits of said address of said branch instruction incremented by one, said value in said upper order bits of said address of said branch instruction decremented by one and said value in said upper order bits of said address of said branch instruction.
7. The method as recited in claim 3, wherein said one of said set of upper order bit value combinations is selected in response to a value in a sign bit and a value in said carry bit in said branch instruction.
8. A system, comprising:
a memory configured to store instructions;
a cache coupled to said memory, wherein said cache is configured to fetch an instruction from said memory; and
an encoding logic unit coupled to said cache, wherein said encoding logic unit is configured to encode said fetched instruction, wherein said encoding logic unit is configured to determine if said instruction is a relative branch instruction, wherein said relative branch instruction stores an offset of a target address comprising n bits, wherein if said instruction is said relative branch instruction then said encoding logic unit is configured to calculate n1 least significant bits of said target address, wherein said encoding logic unit is further configured to replace n1 least significant bits of said offset of said target address with said n1 least significant bits of said target address.
9. The system as recited in claim 8, wherein said encoding logic unit is further configured to append a carry bit to said relative branch instruction thereby increasing a length of said relative branch instruction by one bit.
10. The system as recited in claim 9 further comprises:
a fetch unit coupled to said cache, wherein said fetch unit is configured to calculate a set of upper order bit value combinations of an address of said relative branch instruction.
11. The system as recited in claim 10, wherein said cache is configured to store said relative branch instruction storing said n1 least significant bits of said target address.
12. The system as recited in claim 11 further comprises:
a logic unit coupled to said cache, wherein said logic unit is configured to retrieve said relative branch instruction storing said n1 least significant bits of said target address from said cache.
13. The system as recited in claim 12, wherein said logic unit is further configured to receive said set of upper order bit value combinations of said address of said relative branch instruction from said fetch unit.
14. The system as recited in claim 13, wherein said logic unit is further configured to select a one of said set of upper order bit value combinations of said address of said relative branch instruction.
15. The system as recited in claim 14, wherein said logic unit is further configured to append said selected one of said set of upper order bit value combinations of said address of said relative branch instruction with said n1 least significant bits of said target address to calculate said target address.
16. The system as recited in claim 8, wherein said encoding logic unit is configured to calculate said n1 least significant bits of said target address by adding a value stored in said n1 least significant bits of said offset of said target address stored in said relative branch instruction with a value stored in said n1 least significant bits of said address of said relative branch instruction.
17. The system as recited in claim 10, wherein said set of upper order bit value combinations of said address of said relative branch instruction comprises one or more of the following: a value in said upper order bits of said address of said relative branch instruction incremented by one, said value in said upper order bits of said address of said relative branch instruction decremented by one and said value in said upper order bits of said address of said relative branch instruction.
18. The system as recited in claim 14, wherein said one of said set of upper order bit value combinations is selected in response to a value in a sign bit and a value in said carry bit in said branch instruction.
19. A system, comprising:
means for storing instructions;
means for fetching an instruction;
means for encoding said fetched instruction; and
means for determining if said instruction is a relative branch instruction,
wherein said relative branch instruction stores an offset of a target address comprising n bits, wherein if said instruction is said relative branch instruction then the system further comprises:
means for calculating n1 least significant bits of said target address; and
means for replacing n1 least significant bits of said offset of said target address with said n1 least significant bits of said target address.
20. The system as recited in claim 19 further comprises:
means for appending a carry bit to said relative branch instruction thereby increasing a length of said relative branch instruction by one bit.
21. The system as recited in claim 20 further comprises:
means for calculating a set of upper order bit value combinations of an address of said relative branch instruction.
22. The system as recited in claim 21 further comprises:
means for storing said relative branch instruction storing said n1 least significant bits of said target address.
23. The system as recited in claim 22 further comprises:
means for retrieving said relative branch instruction storing said n1 least significant bits of said target address.
24. The system as recited in claim 23 further comprises:
means for receiving said set of upper order bit value combinations of said address of said relative branch instruction.
25. The system as recited in claim 24 further comprises:
means for selecting a one of said set of upper order bit value combination of said address of said relative branch instruction.
26. The system as recited in claim 25 further comprises:
means for appending said selected one of said set of upper order bit value combination of said address of said relative branch instruction with said n1 least significant bits of said target address to calculate said target address.
27. The system as recited in claim 19, wherein said n1 least significant bits of said target address is calculated by adding a value stored in said n1 least significant bits of said offset of said target address stored in said relative branch instruction with a value stored in said n1 least significant bits of said address of said relative branch instruction.
28. The system as recited in claim 21, wherein said set of upper order bit value combinations of said address of said relative branch instruction comprises one or more of the following: a value in said upper order bits of said address of said relative branch instruction incremented by one, said value in said upper order bits of said address of said relative branch instruction decremented by one and said value in said upper order bits of said address of said relative branch instruction.
29. The system as recited in claim 25, wherein said one of said set of upper order bit value combinations is selected in response to a value in a sign bit and a value in said carry bit in said branch instruction.
30. A processor, comprising:
a cache configured to fetch an instruction; and
an encoding logic unit coupled to said cache configured to encode said fetched instruction, wherein said encoding logic unit is configured to determine if said instruction is a relative branch instruction, wherein said relative branch instruction stores an offset of a target address comprising n bits, wherein if said instruction is said relative branch instruction then said encoding logic unit is configured to calculate n1 least significant bits of said target address, wherein said encoding logic unit is further configured to replace n1 least significant bits of said offset of said target address with said n1 least significant bits of said target address.
31. The processor as recited in claim 30, wherein said encoding logic unit is further configured to append a carry bit to said relative branch instruction thereby increasing a length of said relative branch instruction by one bit.
32. The processor as recited in claim 31 further comprises:
a fetch unit coupled to said cache, wherein said fetch unit is configured to calculate a set of upper order bit value combinations of an address of said relative branch instruction.
33. The processor as recited in claim 32, wherein said cache is configured to store said relative branch instruction storing said n1 least significant bits of said target address.
34. The processor as recited in claim 33 further comprises:
a logic unit coupled to said cache, wherein said logic unit is configured to retrieve said relative branch instruction storing said n1 least significant bits of said target address from said cache.
35. The processor as recited in claim 34, wherein said logic unit is further configured to receive said set of upper order bit value combinations of said address of said relative branch instruction from said fetch unit.
36. The processor as recited in claim 35, wherein said logic unit is further configured to select a one of said set of upper order bit value combinations of said address of said relative branch instruction.
37. The processor as recited in claim 36, wherein said logic unit is further configured to append said selected one of said set of upper order bit value combinations of said address of said relative branch instruction with said n1 least significant bits of said target address to calculate said target address.
38. The processor as recited in claim 30, wherein said encoding logic unit is configured to calculate said n1 least significant bits of said target address by adding a value stored in said n1 least significant bits of said offset of said target address stored in said relative branch instruction with a value stored in said n1 least significant bits of said address of said relative branch instruction.
39. The processor as recited in claim 32, wherein said set of upper order bit value combinations of said address of said relative branch instruction comprises one or more of the following: a value in said upper order bits of said address of said relative branch instruction incremented by one, said value in said upper order bits of said address of said relative branch instruction decremented by one and said value in said upper order bits of said address of said relative branch instruction.
40. The processor as recited in claim 36, wherein said one of said set of upper order bit value combinations is selected in response to a value in a sign bit and a value in said carry bit in said branch instruction.
41. A processor, comprising:
means for fetching an instruction; and
means for determining if said instruction is a relative branch instruction,
wherein said relative branch instruction stores an offset of a target address comprising n bits, wherein if said instruction is said relative branch instruction then the processor further comprises:
means for calculating n1 least significant bits of said target address; and
means for replacing n1 least significant bits of said offset of said target address with said n1 least significant bits of said target address.
42. The processor as recited in claim 41 further comprises:
means for appending a carry bit to said relative branch instruction thereby increasing a length of said relative branch instruction by one bit.
43. The processor as recited in claim 42 further comprises:
means for calculating a set of upper order bit value combinations of an address of said relative branch instruction.
44. The processor as recited in claim 43 further comprises:
means for storing said relative branch instruction storing said n1 least significant bits of said target address.
45. The processor as recited in claim 44 further comprises:
means for retrieving said relative branch instruction storing said n1 least significant bits of said target address.
46. The processor as recited in claim 45 further comprises:
means for receiving said set of upper order bit value combinations of said address of said relative branch instruction from said fetch unit.
47. The processor as recited in claim 46 further comprises:
means for selecting one of said set of upper order bit value combinations of said address of said relative branch instruction.
48. The processor as recited in claim 47 further comprises:
means for appending said selected one of said set of upper order bit value combinations of said address of said relative branch instruction with said n1 least significant bits of said target address to calculate said target address.
49. The processor as recited in claim 41 further comprises:
means for calculating said n1 least significant bits of said target address by adding a value stored in said n1 least significant bits of said offset of said target address stored in said relative branch instruction with a value stored in said n1 least significant bits of said address of said relative branch instruction.
50. The processor as recited in claim 43, wherein said set of upper order bit value combinations of said address of said relative branch instruction comprises one or more of the following: a value in said upper order bits of said address of said relative branch instruction incremented by one, said value in said upper order bits of said address of said relative branch instruction decremented by one and said value in said upper order bits of said address of said relative branch instruction.
51. The processor as recited in claim 47, wherein said one of said set of upper order bit value combinations is selected in response to a value in a sign bit and a value in said carry bit in said branch instruction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Vehicle control system (10), capable of controlling a number of controllable motor vehicle subsystems (30-80) according to at least two preset vehicle operating modes, the control system comprises a central control unit (20) for controlling the motor vehicle subsystems (30-80), and a driver interface (90) with an input arrangement (92) and an output arrangement (94) for selecting operating mode, characterized in that it comprises at least one sensor (100-130) for registering current operating conditions, and that the central control unit (20) is arranged to limit access to at least one of the preset operating modes in response to an output value from at least one sensor (100-130).
2. Vehicle control system (10) according to claim 1, characterized in that it comprises at least one load sensor (100) for registering the load in the vehicle.
3. Vehicle control system (10) according to claim 1, characterized in that it comprises at least one towing sensor (110) arranged to recognize if the vehicle is used for towing a trailer.
4. Vehicle control system (10) according to claim 1, characterized in that it comprises at least one speed sensor (120) arranged to give a signal corresponding to the speed of the vehicle.
5. Vehicle control system (10) according to claim 1, characterized in that it comprises at least one tilting sensor (120) arranged to register tilting of the vehicle.
6. Vehicle control system (10) according to claim 1, characterized in that it comprises at least one controllable accessory system (140-180) and that the central control unit (20) is arranged to limit access to at least one of the preset operating modes in response to a mode of operation of at least one accessory system (140-180).
7. Vehicle control system (10) according to claim 6, characterized in that it comprises a controllable accessory system in the form of a foldable towing hook (140).
8. Vehicle control system (10) according to claim 6, characterized in that the controllable accessory system is in the form of a foldable roof rack (150).
9. Vehicle control system (10) according to claim 1, wherein one of the preset vehicle operating modes is a sport mode, characterized in that the sport mode is not selectable when the load registered by the load sensors (100) exceeds a preset load limit, nor when the towing sensor 110 indicates that there is a trailer hooked onto the towing hook.
10. Vehicle control system (10) according to claim 1, wherein one of the preset vehicle operating modes is a heavy-load mode, characterized in that the heavy-load mode is automatically selected when the load registered by the load sensors 100 exceeds a preset load limit, and when the towing sensor 110 indicates that there is a trailer hooked onto the towing hook.
11. Vehicle control system (10) according to claim 1, wherein one of the preset vehicle operating modes is an off-road mode, characterized in that the vehicle control system 10, in off-road mode, prevents further acceleration when the speed registered by the speed sensor 120 reaches a predefined speed limit, and that off-road mode is locked when the tilting angle registered by the tilting sensor 130 exceeds a predetermined value.
12. Vehicle control system (10) according to claim 1, characterized in that the output arrangement (94) is integrated with a dashboard of display type, and in that the dashboard-image is mode-adapted for each preset operating mode.
13. Automobile, characterized in that it comprises a vehicle control system (10) according to claim 1.
14. Driver interface (90) for controlling a vehicle control system (10), capable of controlling a number of controllable motor vehicle subsystems according to at least two preset vehicle operating modes, characterized in that it comprises a dashboard of display type arranged to display a dashboard-image, and in that the dashboard-image is mode-adapted for each preset operating mode.
15. Driver interface (90) according to claim 14, characterized in that each mode-adapted dashboard-image comprises centrally arranged main section (310) for displaying vital driving related information, and two submenuinformation areas (320a, 320b) adjacent to the main section (310).
16. Driver interface (90) according to claim 15, characterized in that the main section (310) comprises a substantially circular analogue meter (312) for displaying the speed or RPM, a gear field (314) for displaying selected gear, a misc. info field (316) for displaying other information and important alerts, a number of selection fields (340 a-h) disposed along the perimeter of the main section (310), and three shortcut fields (350a-c) at the lower section.
17. Driver interface (90) according to claim 16, characterized in that the selection fields (340a-h) form a part of a menu system used for controlling the features of the vehicle control system (10), and the location relative the center of the main section (310) indicates how each selection field (340a-h) is selected with an input arrangement (92) of the driver interface 90.
18. Driver interface (90) according to claim 17, characterized in that the input arrangement (92) comprises an actuator of joystick type (400), a rotary selector (410) and a push button (420) both arranged on the actuator (400), and three shortcut keys (430) arranged in front of the actuator (400).
19. Driver interface (90) according to claim 18, characterized in that the actuator of joystick type (400) is guided to a number of perimeter positions corresponding to the selection fields of the main section.
20. Driver interface (90) according to claim 19, characterized in that the actuator of joystick type (400) is guided by a force-feedback arrangement.
21. Method of operating a vehicle control system (10), capable of controlling a number of controllable motor vehicle subsystems according to at least two preset vehicle operating modes, the control system (10) comprises a central control unit (20) for controlling the motor vehicle subsystems, and a driver interface (90) for selecting operating mode, characterized by the step of, limiting possible mode selections in accordance with a number of preset operation rules.
22. Method according to claim 21, characterized by the step of registering current operating condition using at least one sensor (100-130), and in that at least one operation rule limit access to at least one of the preset operating modes in response to an output value from at least one sensor (100-130).