1. A display device comprising:
a first substrate;
a switching element formed in a pixel area over the first substrate;
an interlayer insulating film comprising an organic resin formed over the switching element;
a pixel electrode formed over the interlayer insulating film and electrically connected to the switching element;
an alignment film formed over the pixel electrode;
a driver circuit comprising a thin film transistor formed over the first substrate;
a second substrate opposed to the first substrate;
a liquid crystal layer disposed between the first substrate and the second substrate;
a plurality of gap retaining members formed in the pixel area and directly over the driver circuit between the first substrate and the second substrate, wherein the plurality of gap retaining members is formed by a process including:
forming a resin layer; and
patterning the resin layer,
wherein a shape of at least one of the plurality of gap retaining members and a shape of at least another one of the plurality of gap retaining members are different, and
wherein an interval between the gap retaining members in the pixel area is different from an interval between the gap retaining members directly over the driver circuit.
2. The display device according to claim 1 wherein the switching element comprises an inverted staggered thin film transistor.
3. The display device according to claim 1 wherein the resin layer comprises an ultraviolet curable resin.
4. The display device according to claim 1 wherein the resin layer comprises a photocurable polyimide.
5. The display device according to claim 1 wherein at least one of the plurality of gap retaining members has a streamlined shape.
6. The display device according to claim 1 wherein at least one of the plurality of gap retaining members has an ellipse shape.
7. The display device according to claim 1 wherein at least one of the plurality of gap retaining members has a polygon shape.
8. A display device comprising:
a first substrate;
a switching element formed in a pixel area over the first substrate;
an interlayer insulating film comprising an organic resin formed over the switching element;
a pixel electrode formed over the interlayer insulating film and electrically connected to the switching element;
a driver circuit comprising a thin film transistor formed over the first substrate;
a second substrate opposed to the first substrate;
a liquid crystal layer disposed between the first substrate and the second substrate;
a plurality of first gap retaining members formed in the pixel area over the second substrate;
a plurality of second gap retaining members formed over the second substrate, wherein the driver circuit and the plurality of second gap retaining members are overlapped with each other,
wherein an interval between the plurality of first gap retaining members is different from an interval between the plurality of second gap retaining members,
wherein the plurality of first gap retaining members and the plurality of second gap retaining members are formed by a process comprising:
forming a resin layer over the second substrate; and
patterning the resin layer.
9. The display device according to claim 8 wherein the switching element comprises an inverted staggered thin film transistor.
10. The display device according to claim 8 wherein the resin layer comprises an ultraviolet curable resin.
11. The display device according to claim 8 wherein the resin layer comprises a photocurable polyimide.
12. The display device according to claim 8 wherein at least one of the plurality of first gap retaining members and the plurality of second gap retaining members has a different shape from at least one of the plurality of first gap retaining members and the plurality of second gap retaining members.
13. A display device comprising:
a first substrate;
a switching element formed in a pixel area over the first substrate;
an interlayer insulating film comprising an organic resin formed over the switching element;
a pixel electrode formed over the interlayer insulating film and electrically connected to the switching element;
a driver circuit comprising a thin film transistor formed over the first substrate;
a second substrate opposed to the first substrate;
a liquid crystal layer disposed between the first substrate and the second substrate;
a plurality of first gap retaining members formed in the pixel area over the first substrate;
a plurality of second gap retaining members formed over the first substrate, wherein the driver circuit and the plurality of second gap retaining members are overlapped with each other,
wherein an interval between the plurality of first gap retaining members is different from an interval between the plurality of second gap retaining members,
wherein the plurality of first gap retaining members and the plurality of second gap retaining members are formed by a process comprising:
forming a resin layer over the first substrate; and
patterning the resin layer.
14. The display device according to claim 13 wherein the switching element comprises an inverted staggered thin film transistor.
15. The display device according to claim 13 wherein the resin layer comprises an ultraviolet curable resin.
16. The display device according to claim 13 wherein the resin layer comprises a photocurable polyimide.
17. The display device according to claim 13 wherein at least one of the plurality of first gap retaining members and the plurality of second gap retaining members has a different shape from at least one of the plurality of first gap retaining members and the plurality of second gap retaining members.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated MIM capacitor structure suitable for inclusion in a semiconductor device, the capacitor structure comprising:
a first metallization level overlying a substrate, the first metallization level including a first metallization plate overlying a capacitor region of the substrate;
a MIM capacitor, comprising:
the first metallization plate;
a MIM capacitor dielectric overlying the first metallization plate; and
an electrically conductive MIM capacitor plate overlying the MIM capacitor dielectric; and
a parasitic capacitor, comprising:
a second metallization plate comprising a portion of a second metallization level overlying the capacitor region;
a parasitic capacitor dielectric including an interlevel dielectric underlying the second metallization plate; and
a parasitic capacitor plate underlying the interlevel dielectric;
wherein a structure of the first metallization plate is selected from a fingered structure and a convex plate structure, a structure of the second metallization plate is selected from a fingered structure and a convex plate structure, and wherein the fingered structured includes a plurality of conductive fingers extending from a common connector;
wherein the fingered structure includes a plurality of rectangular fingers, each having a finger depth and a finger length, each adjacent pair of fingers separated by a finger spacing; and
wherein a ratio of a finger width to the finger spacing is approximately equal to 4.
2. The capacitor structure of claim 1, wherein the parasitic capacitor plate comprises the MIM capacitor plate.
3. The capacitor structure of claim 2, further comprising:
an electrically conductive via connecting the second metallization plate to the first metallization plate; and
a routing element comprising a portion of the second metallization level, wherein the routing element is connected to the MIM capacitor plate.
4. The capacitive structure of claim 1, wherein a metallization density of the fingered structure is approximately equal to 80%.
5. A semiconductor fabrication process, comprising:
forming a first metallization level overlying a substrate including a capacitor region and a field region, the first metallization level including a first metallization plate overlying the capacitor region;
forming a capacitor dielectric overlying the first metallization plate;
forming a capacitor plate overlying the capacitor dielectric;
forming an interlevel dielectric layer overlying the capacitor plate; and
forming a second metallization level overlying the interlevel dielectric layer, the second metallization level including a second metallization plate overlying the capacitor region;
wherein forming at least one of the first metallization level and the second metallization level includes a patterning of a metallization level to define a fingered structure, the fingered structure including a plurality of electrically coupled finger elements, wherein adjacent finger elements are separated by a minimum spacing;
wherein the finger elements have a finger width; and
wherein a spacing-to-period ratio of the fingered structure is approximately equal to 20%.
6. The semiconductor fabrication process of claim 5, further comprising:
prior to forming the interlevel dielectric layer, forming a second capacitor dielectric overlying the first capacitor plate;
forming a second capacitor plate overlying the second capacitor dielectric.