1. A programmable co-processor system, comprising:
a datapath including a data input, a data output and a plurality of serially connected datapath elements, a first datapath element connected to said data input and a last datapath element connected to said data output, each datapath element receiving data, performing a micro-task upon said data and outputting altered data;
a microprogram memory storing a microprogram comprising a plurality of control words, each control word including a set of signal pattern properties at least partially defining a signal pattern, each control word being associated with one of the tasks and comprising a task identifier identifying that task;
an associated memory storing task-specific data corresponding to the plurality of tasks;
a hardware control module connected said datapath and said microprogram memory, said hardware control module receiving sequentially ordered control words from said microprogram memory and generating one or more signal patterns based on said control words, each signal pattern controlling at least one of said datapath elements, the hardware control module generating the signal pattern associated with a particular control word based on the signal pattern properties included in the particular control word as well as the task-specific data corresponding with the task identified by the particular control word; and
a microcontroller responsive to a modification command to modify the microprogram by modifying one or more of the control words.
2. The system of claim 1, wherein one of the sets of signal pattern properties comprises the phase and period of at least a portion of the associated signal period.
3. A method for processing signals, comprising:
storing a microprogram comprising a plurality of control words, each control word including a set of signal pattern properties at least partially defining a signal pattern, in a microprogram memory;
storing task-specific data in an associated memory, the task-specific data corresponding with a plurality of tasks, wherein each control word is associated with one of the tasks and comprises a task identifier identifying that task;
receiving a modification command at a microcontroller;
translating the received modification command into control information;
modifying the microprogram based on the control information;
performing data processing upon input signals via a datapath comprising a plurality of serially connected datapath elements;
controlling the data processing performed by the datapath by receiving sequentially ordered control words from said microprogram memory and generating one or more signal patterns based on said control words, each signal pattern controlling at least one of said datapath elements to perform a micro-task upon data;
communicating a particular control word and the task-specific data corresponding with the task identified by the particular control word to a hardware control module; and
generating the signal pattern associated with the particular control word based on the signal pattern properties included in the particular control word and the task-specific data corresponding with the task identified by the particular control word.
4. The method of claim 3, wherein:
modifying the microprogram based on the control information comprises modifying one or more of the control words based on the control information.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A storage system comprising:
one or more arrays of physically-addressed solid state disk (paSSD) coupled to a bus, the one or more arrays of paSSDs being addressable using physical addresses associated with data, the data to be stored in the paSSD in blocks, the one or more arrays of paSSD including one or more stripes with each stripe having a segment, at least some of the segments including data and at least some of the segments including parity; and
a non-volatile memory module, the non-volatile memory module including flash tables used to manage blocks in the one or more arrays of paSSD, the flash tables including tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD,
wherein the data to be written to a stripe is kept in the non-volatile memory until a full stripe is available for writing thereby avoiding writing a partial stripe.
2. The storage system of claim 1, further including a central processing unit (CPU) coupled to the one or more arrays of paSSD via the bus.
3. The storage system of claim 2, wherein the CPU is coupled to the non-volatile memory module.
4. The storage system of claim 1, wherein the non-volatile memory module is a flash-backed memory.
5. The storage system, as recited in claim 4, wherein the flash-backed memory includes Dual Inline Memory Module (NV DIMM).
6. The storage system, as recited in claim 1, wherein the non-volatile memory includes magnetic random access memory (MRAM).
7. The storage system of claim 5, wherein the MRAM includes a spin torque transfer MRAM.
8. The storage of claim 1, wherein the at least some of the segments are identified using logical block addresses (LBAs) and the LBAs of a segment are random.
9. The storage of claim 1, further including a stripe table used to identify the physical addresses (PAs) that form at least some of the stripe.
10. The storage of claim 1, wherein the paSSDs further including a flash controller and a subsystem coupled to the flash controller via a flash interface.
11. The storage of claim 9, wherein the flash controller includes a channel controller operable to control the flow of command on the flash interface, the command including physical addresses.
12. The storage of claim 10, wherein the flash controller includes a channel controller operable to control the flow of status on the flash interface.
13. The storage of claim 11, wherein the flash controller includes a channel controller operable to control the flow of data on the flash interface.
14. The storage of claim 12, further including a local buffer, the channel controller operable to save data that is read from the flash subsystem in response to one or more host read commands in a designated page buffer in the local buffer.
15. The storage of claim 13, wherein the channel controller is operable to write to the flash subsystem from the designated page buffer.
16. A method of garbage collection (GC) in a physically-addressed solid state disk (paSSD) comprising:
selecting stripe blocks;
reading a page worth of valid logical block addresses (LBAs) from each paSSD of a stripe that is saved in a designated buffer, the valid LBAs associated with data; and
initiating a write to a destination garbage collection (GC) block from an associated designated buffer.
17. The method of GC of claim 15, further including calculating parity using the data.
18. The method of GC of claim 16, further including sending a calculated parity to an associated paSSD.
19. The method of GC of claim 15, wherein the selecting step is performed by a central processing unit (CPU).
20. The method of GC of claim 15, wherein the reading and initiating steps are performed by a central processing unit (CPU).
21. The method of GC of claim 15, wherein using a stripe table, identifying physical addresses (PAs) that form at least some of the stripe blocks.
22. The method of GC of claim 20, wherein the stripe table is included in a non-volatile memory.
23. The method of GC of claim 21, wherein the CPU is coupled to the non-volatile memory module.
24. The method of GC of claim 21, wherein the non-volatile memory module is a flash-backed memory.
25. The storage system, as recited in claim 21, wherein the non-volatile memory includes magnetic random access memory (MRAM).
26. The storage system of claim 24, wherein the MRAM includes a spin torque transfer MRAM.
27. The storage of claim 1, further wherein the flash tables are substantially periodically saved in the plurality of physically-addressed SSDs, and parts of the flash tables that are updated since a previous save are saved in the non-volatile memory module.
28. The storage of claim 1, further wherein the bus is a Peripheral Component Interconnect Express bus.