1. A clock and data recovery circuit coupled to an input data signal, comprising:
a phase detector, comprising:
a linear phase difference generator circuit having a first input coupled to the input data signal and a second input coupled to a recovered clock signal, the linear phase difference generator circuit having a first phase difference output and a second phase different output, the first phase difference output including a first analog signal that is proportional to the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal, the second phase difference output including a second analog signal that is proportional to the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal; and
an analog sample and hold circuit coupled to the first and second phase difference outputs of the linear phase difference generator for sampling the analog voltage levels of the first and second phase difference outputs in response to a first transition of the input data signal and for holding the sampled analog voltage levels until a second transition of the input data signal, the sampled analog voltage levels respectively providing linear rising and falling information signals;
an averaging circuit that sums the linear rising and falling information signals into a single linear information signal indicative of the relative phase differences between both the rising and falling edges of the input data signal and the recovered clock signal;
a gain block that generates a non-linear control signal from the single linear information signal; and
a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal.
2. The clock and data recovery circuit of claim 1, the phase detector further comprising:
a trigger generation circuit coupled to the input data signal for generating sampling trigger signals for causing the sample and hold circuit to sample the analog voltage levels of the first and second phase difference outputs.
3. The clock and data recovery circuit of claim 1, the phase detector further comprising:
a circuit coupled to the input data signal and the recovered clock signal for generating a retimed data signal.
4. The clock and data recovery circuit of claim 1, wherein the linear phase difference generator comprises a pair of linear D-type flip-flops.
5. The clock and data recovery circuit of claim 4, wherein the pair of linear D-type flip-flops each include a input data node and a input clock node, wherein the recovered clock signal is coupled to the input data node of each of the pair of linear D-type flip-flops, the input data signal is coupled to one of the input clock nodes of the pair of linear D-type flip flops, and an inverted version of the input data signal is coupled to the other one of the input clock nodes of the pair of linear D-type flip flops.
6. The clock and data recovery circuit of claim 1, wherein the sample and hold circuit comprises a first and second sample and hold circuit, the first sample and hold circuit being coupled to the first phase difference output and configured to sample and hold the voltage level of the first phase difference output on a rising edge of the input data signal, and the second sample and hold circuit being coupled to the second phase difference output and configured to sample and hold the voltage level of the second phase difference output on a falling edge of the input data signal.
7. The clock and data recovery circuit of claim 6, further comprising:
a trigger generation circuit coupled to the input data signal for generating sampling trigger signals including a rising trigger signal coupled to the first sample and hold circuit and a falling trigger signal coupled to the second sample and hold circuit.
8. A clock and data recovery circuit coupled to an input data signal, comprising:
a phase detector, comprising:
circuitry for receiving an input data signal and a recovered clock signal and for generating a first analog phase difference signal indicating the phase difference between a rising edge of the input data signal and the recovered clock signal and a second analog phase difference signal indicating the phase difference between a falling edge of the input data signal and the recovered clock signal; and
circuitry for sampling and holding the first and second analog phase difference signals to provide analog up and down information signals;
a filterintegrator circuit coupled to the linear phase detector that combines the analog up and down information signals into a single analog information signal indicative of the relative phase differences between both the rising and falling edges of the input data signal and the recovered clock signal;
a gain block that generates a non-linear control signal from the single analog information signal; and
a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal.
9. The clock and data recovery circuit of claim 8, the linear phase detector further comprising:
circuitry for generating rising and falling trigger signals responsive to the rising and falling edges of the input data signal, the rising and falling trigger signals being coupled to the circuitry for sampling and holding the first and second analog phase difference signals and operating to trigger the sampling and holding of the first and second analog phase difference signals.
10. The clock and data recovery circuit of claim 8, the linear phase detector further comprising:
circuitry for retiming the input data signal in response to the recovered clock signal.
11. The clock and data recovery circuit of claim 8, wherein the circuitry for receiving includes a first and second linear phase difference generator circuit, the first linear phase difference generator circuit being coupled to the recovered clock signal and the input data signal and generating the first analog phase difference signal, and the second linear phase difference generator circuit being coupled to the recovered clock signal an inverted version of the input data signal and generating the second analog phase difference signal.
12. The clock and data recovery circuit of claim 11, wherein the first and second linear phase difference generator circuits are linear D-type flip flops.
13. The clock and data recovery circuit of claim 8, wherein the circuit for sampling and holding comprises a first sample and hold circuit coupled to the first analog phase difference signal and a second sample and hold circuit coupled to the second analog phase difference signal.
14. The clock and data recovery circuit of claim 13, wherein the first sample and hold circuit is triggered on a rising edge of the input data signal and the second sample and hold circuit is triggered on a falling edge of the input data signal.
15. A clock and data recovery circuit coupled to an input data signal, comprising:
a phase detector, comprising:
a pair of linear flip flops configured to sample the recovered clock signal on a rising and a falling edge of the input data signal and to generate a first and a second analog phase difference output voltage;
wherein the first analog phase difference output voltage is proportional to the phase difference between the recovered clock signal and the rising edge of the input data signal, and the second analog phase difference output voltage is proportional to the phase difference between the recovered clock signal and the falling edge of the input data signal; and
a pair of sample and hold circuits configured to sample the first and second analog phase difference output voltages in response to a first transition of the input data signal and to generate linear rising and falling information signals there from which are held until a second transition of the input data signal;
an averaging circuit that sums the linear rising and falling information signals into a single linear information signal indicative of the relative phase differences between both the rising and falling edges of the input data signal and the recovered clock signal;
a gain block that generates a non-linear control signal from the single linear information signal; and
a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal.
16. The clock and data recovery circuit of claim 15, the phase detector further comprising:
a non-linear flip flop coupled to the input data signal and the recovered clock signal for generating a retimed data signal.
17. The clock and data recovery circuit of claim 15, the phase detector further comprising:
a trigger generator for receiving the input data signal and for generating a rising trigger signal and a falling trigger signal; wherein the rising trigger signal causes one of the pair of sample and hold circuits to generate the rising information signal and the falling trigger signal causes the other of the pair of sample and hold circuits to generate the falling information signal.
18. A clock and data recovery circuit coupled to an input data signal, comprising:
a linear sample and hold phase detector coupled to the input data signal and a recovered clock signal for generating linear rising and falling information signals which are analog signals that are indicative of the relative phase differences between the rising and falling edges of the input data signal and the recovered clock signal;
a gain block coupled to the linear rising and falling information signals for generating a non-linear control signal;
a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal; and
an averaging circuit coupled between the linear sample and hold phase detector and the gain block for summing the linear rising and falling information signals into a single linear information signal indicative of the relative phase differences between both the rising and falling edges of the input data signal and the recovered clock signal.
19. The clock and data recovery circuit of claim 18, wherein the linear sample and hold phase detector includes a retiming circuit for generating a retimed data signal from the input data signal and the recovered clock signal.
20. The clock and data recovery circuit of claim 18, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a frequency control signal; and
a buffer coupled to the non-linear control signal for generating a phase control signal;
wherein the frequency control signal and the phase control signal are coupled to the voltage controlled oscillator and are used to generate the recovered clock signal.
21. The clock and data recovery circuit of claim 18, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a VCO control signal;
wherein the VCO control signal is coupled to the voltage controlled oscillator for generating the recovered clock signal.
22. A clock and data recovery circuit coupled to an input data signal, comprising:
a linear phase detector coupled to the input data signal and a recovered clock signal for generating analog up and down information signals indicative of the relative phase differences between the rising and falling edges of the input data signal and the recovered clock signal;
a gain block coupled to the analog up and down information signals for generating a non-linear control signal;
a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal; and
a filterintegrator circuit coupled between the linear phase detector and the gain block for combining the analog up and down information signals into a single analog information signal indicative of the relative phase differences between both the rising and falling edges of the input data signal and the recovered clock signal.
23. The clock and data recovery circuit of claim 22, wherein the linear phase detector includes a retiming circuit for generating a retimed data signal from the input data signal and the recovered clock signal.
24. The clock and data recovery circuit of claim 22, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a frequency control signal; and
a buffer coupled to the non-linear control signal for generating a phase control signal;
wherein the frequency control signal and the phase control signal are coupled to the voltage controlled oscillator and are used to generate the recovered clock signal.
25. The clock and data recovery circuit of claim 22, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a VCO control signal;
wherein the VCO control signal is coupled to the voltage controlled oscillator for generating the recovered clock signal.
26. A phase locked loop circuit coupled to an input reference clock, comprising:
a linear sample and hold phase detector coupled to the input reference clock and a recovered clock signal for generating linear rising and falling information signals which are analog signals that are indicative of the relative phase differences between the rising and falling edges of the input reference clock and the recovered clock signal;
a gain block coupled to the linear rising and falling information signals for generating a non-linear control signal;
a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal; and
an averaging circuit coupled between the linear sample and hold phase detector and the gain block for summing the linear rising and falling information signals into a single linear information signal indicative of the relative phase differences between both the rising and falling edges of the input reference clock and the recovered clock signal.
27. The phase locked loop circuit of claim 26, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a frequency control signal; and
a buffer coupled to the non-linear control signal for generating a phase control signal:
wherein the frequency control signal and the phase control signal are coupled to the voltage controlled oscillator and are used to generate the recovered clock signal.
28. The phase locked loop circuit of claim 26, further comprising:
a frequency divider coupled to an output of the voltage controlled oscillator, wherein the recovered clock signal is a frequency divided version of the output of the voltage controlled oscillator.
29. The phase locked loop circuit of claim 26, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a VCO control signal;
wherein the VCO control signal is coupled to the voltage controlled oscillator for generating the recovered clock signal.
30. A phase locked loop circuit coupled to a reference clock signal, comprising:
a linear phase detector coupled to the reference clock signal and a recovered clock signal for generating analog up and down information signals indicative of the relative phase differences between the rising and falling edges of the reference clock signal and the recovered clock signal;
a gain block coupled to the analog up and down information signals for generating a non-linear control signal;
a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal; and
a filterintegrator circuit coupled between the linear phase detector and the gain block for combining the analog up and down information signals into a single analog information signal indicative of the relative phase differences between both the rising and falling edges of the reference clock signal and the recovered clock signal.
31. The phase locked loop circuit of claim 30, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a frequency control signal; and
a buffer coupled to the non-linear control signal for generating a phase control signal;
wherein the frequency control signal and the phase control signal are coupled to the voltage controlled oscillator and are used to generate the recovered clock signal.
32. The phase locked loop circuit of claim 30, further comprising:
a frequency divider coupled to an output of the voltage controlled oscillator, wherein the recovered clock signal is a frequency divided version of the output of the voltage controlled oscillator.
33. The phase locked loop circuit of claim 30, further comprising:
a charge pump and loop filter circuit coupled to the non-linear control signal for generating a VCO control signal;
wherein the VCO control signal is coupled to the voltage controlled oscillator for generating the recovered clock signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first insulating layer formed on the semiconductor substrate;
a first electrode formed on the first insulating layer;
an interlayer dielectric formed over the first electrode;
a wiring layer formed over the interlayer dielectric;
a barrier metal layer formed on an inner surface of a first contact hole;
a second insulating layer formed over the first electrode; and
a second electrode formed on the second insulating layer,
wherein the first contact hole is formed between the first electrode and the wiring layer, to pass through the first electrode and the interlayer dielectric, and to terminate at an inside of the first insulating layer, and
wherein a second contact hole is formed above the first insulating layer so as to be connected to the second electrode.
2. A semiconductor device according to claim 1, wherein the first insulating layer is an element-isolation region, which isolates adjacent semiconductor elements.
3. A semiconductor device according to claim 1, wherein the barrier metal layer is of a material selected from Ti, W, Mo, TiSi, TiN, TiW and WSi.
4. A semiconductor device according to claim 3, wherein the barrier metal layer is of Ti (titanium) and the first electrode is of Poly-Silicon.
5. A semiconductor device according to claim 1, wherein the barrier metal layer is alloyed with the first electrode.
6. A semiconductor device according to claim 1, wherein the barrier metal layer is alloyed with the first electrode by an RTN (Rapid Thermal Nitridation) process.
7. A semiconductor device according to claim 1, wherein the first contact hole is formed by a two-step process, in which an intermediate hole is formed to an upper surface of the first insulating layer in a first step and the first contact hole is completed in a second step.
8. A semiconductor device according to claim 7, wherein the first and second steps are of etching process with different process conditions.
9. A semiconductor device according to claim 1, wherein the first electrode is a lower gate of a capacitor, and the second electrode is an upper gate of a capacitor.
10. A semiconductor device according to claim 1, further comprising: a non-volatile memory cell formed on the semiconductor substrate.
11. A semiconductor device according to claim 10, wherein the non-volatile memory cell includes
a source region formed on the semiconductor substrate;
a drain region formed on the semiconductor substrate;
a tunnel oxide layer formed over the source and drain regions;
a second contact hole formed through the interlayer dielectric between one of the source and drain regions and the wiring layer; and
a third contact hole formed through the interlayer dielectric between one of the source and drain regions and the wiring layer.
12. A semiconductor device according to claim 1, wherein the second insulating layer is superposed between the first electrode and the second electrode.
13. A semiconductor device according to claim 1, wherein at least a portion of the second electrode is directly over the first electrode.
14. A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate;
forming a first insulating layer on the semiconductor substrate;
forming a first electrode on the first insulating layer;
forming an interlayer dielectric over the first electrode;
forming a first contact hole to pass through the first electrode and the interlayer dielectric, and to terminate at an inside of the first insulating layer;
forming a barrier metal layer on an inner surface of the first contact hole;
forming a wiring layer on the first contact hole so that the wiring layer is electrically coupled to the first electrode;
forming a second insulating layer over the first electrode;
forming a second electrode on the second insulating layer; and
forming a second contact hole above the first insulating layer so as to be connected to the second electrode.
15. A method for fabricating a semiconductor device according to claim 14, further comprising: alloying the barrier metal layer with the first electrode.
16. A method for fabricating a semiconductor device according to claim 15, wherein the barrier metal layer is alloyed with the first electrode by an RTN (Rapid Thermal Nitridation) process.
17. A method for fabricating a semiconductor device according to claim 14, wherein the first insulating layer is an element-isolation region formed by LOCOS technique.
18. A method for fabricating a semiconductor device according to claim 14, wherein the first electrode is a lower gate of a capacitor, and the second electrode is an upper gate of a capacitor.
19. A method for fabricating a semiconductor device according to claim 14, wherein the barrier metal layer is of a material selected from Ti, W, Mo, TiSi, TiN, TiW and WSi.
20. A method for fabricating a semiconductor device according to claim 14, wherein the barrier metal layer is of Ti (titanium) and the first electrode is of Poly-Silicon.
21. A method for fabricating a semiconductor device according to claim 14, wherein the step forming the first contact hole includes
forming an intermediate hole to an upper surface of the first insulating layer; and
completing the first contact hole to get into the first insulating layer.
22. A method for fabricating a semiconductor device according to claim 21, wherein the step forming the first contact hole is carried out by two step of etching process with different conditions.
23. A method for fabricating a semiconductor device according to claim 14, further comprising: forming a non-volatile memory cell on the semiconductor substrate.
24. A method for fabricating a semiconductor device according to claim 23, wherein the non-volatile memory cell includes
a source region formed on the semiconductor substrate;
a drain region formed on the semiconductor substrate;
a tunnel oxide layer formed over the source and drain regions;
a second contact hole formed through the interlayer dielectric between one of the source and drain regions and the wiring layer; and
a third contact hole formed through the interlayer dielectric between one of the source and drain regions and the wiring layer.
25. A semiconductor device according to claim 13, wherein at least a portion of the second insulating layer is disposed directly over the first electrode, and directly under the second electrode.