1. A polyolefin resin composition comprising 25 to 70 weight percent of polyolefin resin and 75 to 30 weight percent of an inorganic filler wherein the polyolefin resin comprises 40 to 80 weight percent of polyethylene resin and 60 to 20 weight percent of polypropylene, and the polyethylene resin comprises 60 to 98 weight percent of a linear low-density polyethylene and 40 to 2 weight percent of a branched low-density polyethylene.
2. A polyolefin resin composition as described in claim 1 containing 0.5 to 5 weight parts of a hardened castor oil and 0.5 to 5 weight parts of a dehydrated castor oil to 100 weight parts of the resin composition.
3. A polyolefin rein composition as described in claim 1 containing 0.5 to 5 weight parts of a liquid ethylene-olefin oligomer to 100 weight parts of the resin composition.
4. A polyolefin film made of the polyolefin resin composition as described in claim 1.
5. A polyolefin film as described in claim 4 wherein the basis weight is from 15 to 60 gm2, the tensile elongation at break per 1 gm2 in a TD direction is at least 12.5%(gm2), and the tensile strength per 1 gm2is at least 17 g25 mm(gm2).
6. A porous film prepared by stretching the polyolefin film as described in claim 4.
7. A porous film as described in claim 6 wherein the basis weight is from 15 to 50 gm2 and the vapor permeability is at least 500 gm224 hr.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor device comprising:
at least one trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a trench;
a first drain region positioned under a bottom surface of the trench;
first source regions positioned on both sides of the trench;
an extended drain region positioned between the first drain region and the first source regions;
a first drain electrode connected electrically to the first drain region; and
first source electrodes connected electrically to corresponding first source regions; and
at least one planar MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate;
a second drain region and a second source region that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode;
a second drain electrode connected electrically to the second drain region; and
a second source electrode connected electrically to the second source region,
wherein the first drain electrode, the first source electrodes, the second drain electrode, and the second source electrode are formed by patterning a same metal layer.
2. The semiconductor device according to claim 1, wherein the first gate electrodes and the second gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench.
3. The semiconductor device according to claim 1, wherein an n-channel trench lateral power MOSFET and a p-channel trench lateral power MOSFET are positioned on the semiconductor substrate.
4. The semiconductor device according to claim 1, wherein the at least one trench lateral power MOSFET is positioned in a well region that is positioned in the semiconductor substrate.
5. The semiconductor device according to claim 4, wherein a plurality of trench lateral power MOSFETs of a positioned in the same well region.
6. The semiconductor device according to claim 1, wherein an n-channel planar MOSFET and a p-channel planar MOSFET are positioned on the semiconductor substrate.
7. The semiconductor device according to claim 1, wherein a bipolar transistor is positioned on the semiconductor substrate, and a collector electrode, a base electrode, and an emitter electrode of the bipolar transistor are formed by patterning the metal layer.
8. The semiconductor device according to claim 1, wherein a resistance element is positioned on the semiconductor substrate, and electrodes of the resistance element are formed by patterning the metal layer.
9. The semiconductor device according to claim 2, wherein a capacitance element is positioned on the semiconductor substrate, and an electrode of the capacitance element is formed by patterning the polysilicon layer.
10. A manufacturing method of a semiconductor device comprising at least one trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a trench, a first drain region positioned under a bottom surface of the trench, first source regions positioned on both sides of the trench, an extended drain region positioned between the first drain region and the first source regions, a first drain electrode connected electrically to the first drain region, and first source electrodes connected electrically to the respective first source regions, and at least one planar MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate, a second drain region and a second source region that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode, a second drain electrode connected electrically to the second drain region, and a second source electrode connected electrically to the second source region, the manufacturing method comprising:
forming the trench in the semiconductor substrate;
forming the extended drain region;
forming the first gate oxide film and the second gate oxide film;
forming first gate electrodes and the second gate electrode;
forming the first drain region, first source regions, the second drain region, and the second source region;
laying an interlayer insulating film over the surface of the semiconductor substrate;
etching the interlayer insulating film to expose the first drain region under the bottom surface of the trench;
filling the inside of the trench with a polysilicon layer that is in contact with the first drain region;
laying a passivation film over the surface of the semiconductor substrate;
etching the passivation film and the interlayer insulating film to expose the polysilicon layer, the first source regions, the second drain region, and the second source region; and
laying a metal layer on the passivation film and patterning the metal layer to form the first drain electrode, first source electrodes, the second drain electrode, and the second source electrode that are in contact with the polysilicon layer, the first source regions, the second drain region, and the second source region, respectively.
11. The manufacturing method according to claim 10, wherein the polysilicon layer is laid over the surface of the semiconductor substrate after the first gate oxide film and the second gate oxide film have been formed, and then the polysilicon layer is patterned to form the first gate electrodes and the second gate electrode simultaneously.
12. The manufacturing method according to claim 10, wherein the first gate oxide film and the second gate oxide film are formed simultaneously by forming an oxide film over the surface of the semiconductor substrate after the extended drain region has been formed.
13. The manufacturing method according to claim 10, wherein a well region is formed in the semiconductor substrate, and then the trench is formed in the well region.
14. The manufacturing method according to claim 10, wherein after the trench is formed in the semiconductor substrate, impurity diffusion is performed through the trench to form a well region that surrounds the trench.
15. The manufacturing method according to claim 10, wherein selective oxidation films for device isolation are formed after the trench has been formed in the semiconductor substrate.
16. The manufacturing method according to claim 10, wherein the trench is formed after selective oxidation films for device isolation have been formed on the semiconductor substrate.
17. A semiconductor device comprising:
a trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a trench;
a first source region of a second conductivity type positioned under a bottom surface of the trench;
first drain regions of a second conductivity type positioned on both sides of the trench;
an extended drain region of a second conductivity type and a base region of a first conductivity type to serve as channel regions, the extended drain region and the base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions; and
a first source electrode connected electrically to the first source region;
a first planar MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate;
a second drain region of a first conductivity type and a second source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode;
a second drain electrode connected electrically to the second drain region; and
a second source electrode connected electrically to the second source region; and
a second planar MOSFET positioned on the semiconductor substrate, comprising
a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate;
a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the third gate electrode;
a third drain electrode connected electrically to the third drain region; and
a third source electrode connected electrically to the third source region,
wherein the first drain electrodes, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are formed by patterning the same metal layer.
18. The semiconductor device according to claim 17, wherein the first gate electrodes, the second gate electrode, and the third gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench.
19. The semiconductor device according to claim 17, further comprising a body region that is positioned under the bottom surface of the trench and has a same conductivity type as the base region.
20. The semiconductor device according to claim 17, further comprising a barrier metal layer and a conductor that is one of an n-type or p-type semiconductor extending in the trench from the surface of the semiconductor substrate proximate to the bottom surface of the trench, wherein the first source electrode is in contact with the conductor, the conductor is in contact with the barrier metal layer, and the barrier metal layer is in contact with the first source region..
21. The semiconductor device according to claim 20, further comprising a plug region that is positioned under the bottom surface of the trench and has a same conductivity type as the base region, wherein the barrier metal layer is in contact with the plug region.
22. The semiconductor device according to claim 19, further comprising body regions that are positioned on both sides of the trench and have the same conductivity type as the base region.
23. A semiconductor device comprising:
a first trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a first trench;
a first source region of a second conductivity type positioned under a bottom surface of the first trench;
first drain regions of a second conductivity type positioned on both sides of the first trench;
a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions; and
a first source electrode connected electrically to the first source region;
a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and second gate electrodes that are positioned in a second trench;
a second source region of a first conductivity type positioned under a bottom surface of the second trench;
second drain regions of a first conductivity type positioned on both sides of the second trench;
a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;
second drain electrodes connected electrically to the respective second drain regions; and
a second source electrode connected electrically to the second source region; and
a planar MOSFET positioned on the semiconductor substrate, comprising
a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;
a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;
a third drain electrode connected electrically to the third drain region; and
a third source electrode connected electrically to the third source region,
wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, and the third source electrode are formed by patterning a same metal layer.
24. The semiconductor device according to claim 23, wherein the first gate electrodes, the second gate electrodes, and the third gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench.
25. The semiconductor device according to claim 23, further comprising a first body region that is positioned under the bottom surface of the first trench and has a same conductivity type as the first base region.
26. The semiconductor device according to claim 25, further comprising a second body region that is positioned under the bottom surface of the second trench and has a same conductivity type as the second base region.
27. The semiconductor device according to claim 23, further comprising first and second barrier metal layers, a first conductor that is an n-type or p-type semiconductor extending in the first trench from the surface of the semiconductor substrate proximate to the bottom surface of the first trench, and a second conductor that is one of an n-type or p-type semiconductor extending in the second trench from the surface of the semiconductor substrate proximate to the bottom surface of the second trench, wherein the first source electrode is in contact with the first conductor, the first conductor is in contact with the first barrier metal layer, and the first barrier metal layer is in contact with the first source region, and wherein the second source electrode is in contact with the second conductor, the second conductor is in contact with the second barrier metal layer, and the second barrier metal layer is in contact with the second source region.
28. The semiconductor device according to claim 25, further comprising body regions that are positioned on both sides of the first trench and have the same conductivity type as the first base region.
29. The semiconductor device according to claim 26, further comprising body regions that are positioned on both sides of the second trench and have the same conductivity type as the second base region.
30. A semiconductor device comprising:
a first trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a first trench;
a first source region of a second conductivity type positioned under a bottom surface of the first trench;
first drain regions of a second conductivity type positioned on both sides of the first trench;
a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions; and
a first source electrode connected electrically to the first source region;
a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and second gate electrodes that are positioned in a second trench;
a second source region of a first conductivity type positioned under a bottom surface of the second trench;
second drain regions of a first conductivity type positioned on both sides of the second trench;
a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;
second drain electrodes connected electrically to the respective second drain regions; and
a second source electrode connected electrically to the second source region;
a first planar MOSFET positioned on the semiconductor substrate, comprising
a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;
a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;
a third drain electrode connected electrically to the third drain region; and
a third source electrode connected electrically to the third source region; and
a second planar MOSFET positioned on the semiconductor substrate, comprising
a fourth gate oxide film and a fourth gate electrode that are positioned on the surface of the semiconductor substrate;
a fourth drain region of a first conductivity type and a fourth source region of a first conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the fourth gate electrode;
a fourth drain electrode connected electrically to the fourth drain region; and
a fourth source electrode connected electrically to the fourth source region,
wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode are formed by patterning a same metal layer.
31. The semiconductor device according to claim 30, wherein the first gate electrodes, the second gate electrodes, the third gate electrode, and the fourth gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench.
32. The semiconductor device according to claim 30, further comprising a first body region that is positioned under the bottom surface of the first trench and has a same conductivity type as the first base region.
33. The semiconductor device according to claim 32, further comprising a second body region that is positioned under the bottom surface of the second trench and has a same conductivity type as the second base region.
34. The semiconductor device according to claim 30, further comprising first and second barrier metal layers, a first conductor that is an n-type or p-type semiconductor extending in the first trench from the surface of the substrate proximate to the bottom surface of the first trench, and a second conductor that is one of an n-type or p-type semiconductor extending in the second trench from the surface of the substrate proximate to the bottom surface of the second trench, wherein the first source electrode is in contact with the first conductor, the first conductor is in contact with the first barrier metal layer, and the first barrier metal layer is in contact with the first source region, and wherein the second source electrode is in contact with the second conductor, the second conductor is in contact with the second barrier metal layer, and the second barrier metal layer is in contact with the second source region.
35. The semiconductor device according to claim 32, further comprising body regions that are positioned on both sides of the first trench and have a same conductivity type as the first base region.
36. The semiconductor device according to claim 33, further comprising body regions that are positioned on both sides of the second trench and have a same conductivity type as the second base region.
37. A manufacturing method of a semiconductor device comprising a trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a trench; a first source region of a second conductivity type positioned under a bottom surface of the trench; first drain regions of a second conductivity type positioned on both sides of the trench; an extended drain region of a second conductivity type and a base region of a first conductivity type to serve as channel regions, the extended drain region and the base region being positioned between the first source region and the first drain regions; first drain electrodes connected electrically to the respective first drain regions; and a first source electrode connected electrically to the first source region; a first planar MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate; a second drain region of a first conductivity type and a second source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode; a second drain electrode connected electrically to the second drain region; and a second source electrode connected electrically to the second source region; and a second planar MOSFET positioned on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate; a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode; a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region, the manufacturing method comprising:
forming the extended drain region in a semiconductor substrate;
forming the trench;
forming the base region and the channel region of the second planar MOSFET simultaneously;
forming the channel region of the first planar MOSFET;
forming the first gate oxide film, the second gate oxide film, and the third gate oxide film;
forming first gate electrodes, the second gate electrode, and the third gate electrode;
forming first drain regions, the first source region, the third drain region, and the third source region simultaneously;
forming the second drain region and the second source region simultaneously;
laying an interlayer insulating film over the surface of the semiconductor substrate, and etching the interlayer insulating film to expose the first source region at the bottom of the trench;
filling the inside of the trench with a polysilicon layer that is in contact with the first source region;
laying a passivation film over the surface of the semiconductor substrate, and etching the passivation film and the interlayer insulating film to expose the first drain regions, the polysilicon layer, the second drain region, the second source region, the third drain region, and the third source region; and
laying a metal layer on the passivation film and patterning the metal layer to form first drain electrodes, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode that are in contact with the first drain regions, the polysilicon layer, the second drain region, the second source region, the third drain region, and the third source region, respectively.
38. The manufacturing method according to claim 37, wherein the polysilicon layer is laid over the surface of the semiconductor substrate after the first gate oxide film, the second gate oxide film, and the third gate oxide film have been formed, and then the polysilicon layer is patterned to form the first gate electrodes, the second gate electrode, and the third gate electrode simultaneously.
39. The manufacturing method according to claim 37, wherein the first gate oxide film, the second gate oxide film, and the third gate oxide film are formed simultaneously.
40. The manufacturing method according to claim 37, wherein a body region having a same conductivity type as the base region is formed under the bottom surface of the trench after the trench has been formed and before the base region and the channel region of the second planar MOSFET are formed.
41. The manufacturing method according to claim 37, wherein the trench is formed after selective oxidation films for isolating the trench lateral power MOSFET, the first planar MOSFET, and the second planar MOSFET from each other have been formed.
42. A manufacturing method of a semiconductor device comprising a trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a trench; a first source region of a second conductivity type positioned under a bottom surface of the trench; first drain regions of a second conductivity type positioned on both sides of the trench; an extended drain region of a second conductivity type and a base region of a first conductivity type to serve as channel regions, the extended drain region and the base region being positioned between the first source region and the first drain regions; first drain electrodes connected electrically to the respective first drain regions; and a first source electrode connected electrically to the first source region; a first planar MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate; a second drain region of a first conductivity type and a second source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode; a second drain electrode connected electrically to the second drain region; and a second source electrode connected electrically to the second source region; and a second planar MOSFET on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate; a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode; a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region, the manufacturing method comprising:
forming the trench in a semiconductor substrate;
forming a well region of a first conductivity type that surrounds the trench by implanting an impurity into a region of the trench lateral power MOSFET and diffusing the implanted impurity;
forming the extended drain region;
forming the base region and the channel region of the second planar MOSFET simultaneously;
forming the channel region of the first planar MOSFET;
forming the first gate oxide film, the second gate oxide film, and the third gate oxide film;
forming first gate electrodes, the second gate electrode, and the third gate electrode;
forming first drain regions, the first source region, the third drain region, and the third source region simultaneously;
forming the second drain region and the second source region simultaneously;
laying an interlayer insulating film over the surface of the semiconductor substrate, and etching the interlayer insulating film to expose the first source region at the bottom of the trench;
filling the inside of the trench with a polysilicon layer that is in contact with the first source region;
laying a passivation film over the surface of the semiconductor substrate, and etching the passivation film and the interlayer insulating film to expose the first drain regions, the polysilicon layer, the second drain region, the second source region, the third drain region, and the third source region; and
laying a metal layer on the passivation film and patterning the metal layer to form first drain electrodes, a first source electrode, a second drain electrode, a second source electrode, a third drain electrode, and a third source electrode that are in contact with the first drain regions, the polysilicon layer, the second drain region, the second source region, the third drain region, and the third source region, respectively.
43. A manufacturing method of a semiconductor device comprising a trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a trench; a first source region of a second conductivity type positioned under a bottom surface of the trench; first drain regions of a second conductivity type positioned on both sides of the trench; an extended drain region of a second conductivity type and a base region of a first conductivity type to serve as channel regions, the extended drain region and the base region being positioned between the first source region and the first drain regions; first drain electrodes connected electrically to the respective first drain regions; and a first source electrode connected electrically to the first source region; a first planar MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate; a second drain region of a first conductivity type and a second source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode; a second drain electrode connected electrically to the second drain region; and a second source electrode connected electrically to the second source region; and a second planar MOSFET positioned on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate; a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode; a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region, the manufacturing method comprising:
forming the extended drain region in the semiconductor substrate;
forming the trench;
forming the base region and the channel region of the second planar MOSFET simultaneously;
forming the channel region of the first planar MOSFET;
forming the first gate oxide film, the second gate oxide film, and the third gate oxide film;
forming first gate electrodes, the second gate electrode, and the third gate electrode;
forming first drain regions, the first source region, the third drain region, and the third source region simultaneously;
forming the second drain region and the second source region simultaneously;
laying an interlayer insulating film over the surface of the semiconductor substrate, and etching the interlayer insulating film to expose the first source region at the bottom of the trench;
forming, in the trench, a barrier metal layer that is in contact with the first source region;
filling the inside of the trench with a polysilicon layer that is in contact with the barrier metal layer;
laying a passivation film over the surface of the semiconductor substrate, and etching the passivation film and the interlayer insulating film to expose the first drain regions, the polysilicon layer, the second drain region, the second source region, the third drain region, and the third source region; and
laying a metal layer on the passivation film and patterning the metal layer to form first drain electrodes, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode that are in contact with the first drain regions, the polysilicon layer, the second drain region, the second source region, the third drain region, and the third source region, respectively.
44. The manufacturing method according to claim 43, wherein a plug region is formed under the bottom surface of the trench after the first gate electrodes, the second gate electrode, and the third gate electrode have been formed and before the interlayer insulating film is formed over the surface of the semiconductor substrate, then the interlayer insulating film is etched to expose the plug region at the bottom of the trench, and then the barrier metal layer is brought into contact with the plug region.
45. The manufacturing method according to claim 43, including forming body regions having a same conductivity type as the base region and then forming extended drain regions having a different conductivity type than the base region by double diffusion on both sides of the trench after the trench has been formed and before the base region and the channel region of the second planar MOSFET are formed.
46. A manufacturing method of a semiconductor device comprising a first trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a first trench; a first source region of a second conductivity type positioned under a bottom surface of the first trench; first drain regions of a second conductivity type positioned on both sides of the first trench; a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions; first drain electrodes connected electrically to the respective first drain regions; and a first source electrode connected electrically to the first source region; a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and second gate electrodes that are positioned in a second trench; a second source region of a first conductivity type positioned under a bottom surface of the second trench; second drain regions of a first conductivity type positioned on both sides of the second trench; a second extended drain region of a second conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions; second drain electrodes connected electrically to the respective second drain regions; and a second source electrode connected electrically to the second source region; and a planar MOSFET positioned on the same semiconductor substrate as the first trench lateral power MOSFET, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate; a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode; a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region, the manufacturing method comprising:
forming the first extended drain region and the second extended drain region in the semiconductor substrate;
forming the first trench and the second trench;
implanting an impurity of a first conductivity type into a region to become the first base region and a region to become the channel region of the planar MOSFET simultaneously;
implanting an impurity of a second conductivity type into a region to become the second base region;
diffusing the implanted impurities to form the first base region, the second base region, and the channel region of the planar MOSFET simultaneously;
forming the first gate oxide film, the second gate oxide film, and the third gate oxide film;
forming first gate electrodes, second gate electrodes, and the third gate electrode;
implanting an impurity of the second conductivity type into regions to become first drain regions, a region to become the first source region, a region to become the third drain region, and a region to become the third source region simultaneously;
implanting an impurity of the first conductivity type into regions to become second drain regions and a region to become the second source region;
diffusing the implanted impurities to form the first drain regions, the first source region, the second drain regions, the second source region, the third drain region, and the third source region simultaneously;
laying an interlayer insulating film over the surface of the semiconductor substrate, and etching the interlayer insulating film to expose the first source region and the second source region at the bottoms of the first trench and the second trench, respectively;
filling the insides of the first trench and the second trench with a first polysilicon layer and a second polysilicon layer that are in contact with the first source region and the second source region, respectively;
laying a passivation film over the surface of the semiconductor substrate, and etching the passivation film and the interlayer insulating film to expose the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, and the third source region; and
laying a metal layer on the passivation film and patterning the metal layer to form first drain electrodes, the first source electrode, second drain electrodes, the second source electrode, the third drain electrode, and the third source electrode that are in contact with the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, and the third source region, respectively.
47. The manufacturing method according to claim 46, wherein the first polysilicon layer is laid over the surface of the semiconductor substrate after the first gate oxide film, the second gate oxide film, and the third gate oxide film have been formed, and then the first polysilicon layer is patterned to form the first gate electrodes, the second gate electrodes, and the third gate electrode simultaneously.
48. The manufacturing method according to claim 46, wherein the first gate oxide film, the second gate oxide film, and the third gate oxide film are formed simultaneously.
49. The manufacturing method according to claim 46, wherein a body region having the same conductivity type as the first base region is formed under the bottom surface of the first trench after the first trench has been formed and before the impurity of the first conductivity type is implanted into the region to become the first base region and the region to become the channel region of the planar MOSFET.
50. The manufacturing method according to claim 46, wherein a body region having the same conductivity type as the second base region is formed under the bottom surface of the second trench after the second trench has been formed and before the impurity of the second conductivity type is implanted into the region to become the second base region.
51. A manufacturing method of a semiconductor device comprising a first trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a first trench; a first source region of a second conductivity type positioned under a bottom surface of the first trench; first drain regions of a second conductivity type positioned on both sides of the first trench; a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions; first drain electrodes connected electrically to the respective first drain regions; and a first source electrode connected electrically to the first source region; a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and second gate electrodes that are positioned in a second trench; a second source region of a first conductivity type positioned under a bottom surface of the second trench; second drain regions of a first conductivity type positioned on both sides of the second trench; a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions; second drain electrodes connected electrically to the respective second drain regions; and a second source electrode connected electrically to the second source region; and a planar MOSFET positioned on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate; a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode; a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region, the manufacturing method comprising:
forming the first extended drain region and the second extended drain region in the semiconductor substrate;
forming the first trench and the second trench;
implanting an impurity of the first conductivity type into a region to become the first base region and a region to become the channel region of the planar MOSFET simultaneously;
implanting an impurity of the second conductivity type into a region to become the second base region;
diffusing the implanted impurities to form the first base region, the second base region, and the channel region of the planar MOSFET simultaneously;
forming the first gate oxide film, the second gate oxide film, and the third gate oxide film;
forming first gate electrodes, second gate electrodes, and the third gate electrode;
implanting an impurity of the second conductivity type into regions to become first drain regions, a region to become the first source region, a region to become the third drain region, and a region to become the third source region simultaneously;
implanting an impurity of the first conductivity type into regions to become second drain regions and a region to become the second source region;
diffusing the implanted impurities to form the first drain regions, the first source region, the second drain regions, the second source region, the third drain region, and the third source region simultaneously;
laying an interlayer insulating film over the surface of the semiconductor substrate, and etching the interlayer insulating film to expose the first source region and the second source region at the bottoms of the first trench and the second trench, respectively;
forming, in the first trench and the second trench, a first barrier metal layer and a second barrier metal layer that are in contact with the first source region and the second source region, respectively;
filling the insides of the first trench and the second trench with a first polysilicon layer and a second polysilicon layer that are in contact with the first barrier metal layer and the second barrier metal layer, respectively;
laying a passivation film over the surface of the semiconductor substrate, and etching the passivation film and the interlayer insulating film to expose the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, and the third source region; and
laying a metal layer on the passivation film and patterning the metal layer to form first drain electrodes, a first source electrode, second drain electrodes, a second source electrode, a third drain electrode, and a third source electrode that are in contact with the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, and the third source region, respectively.
52. The manufacturing method according to claim 49, including forming body regions having the first conductivity type and then forming extended drain regions having the second conductivity type by double diffusion on both sides of the first trench after the first . trench has been formed and before the impurity of the first conductivity type is implanted into the region to become the first base region and the region to become the channel region of the planar MOSFET.
53. The manufacturing method according to claim 50, including forming body regions having the second conductivity type and then forming extended drain regions having the first conductivity type by double diffusion on both sides of the second trench after the second trench has been formed and before the impurity of the second conductivity type is implanted into the region to become the second base region.
54. A manufacturing method of a semiconductor device comprising a first trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a first trench; a first source region of a second conductivity type positioned under a bottom surface of the first trench; first drain regions of a second conductivity type positioned on both sides of the first trench; a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions; first drain electrodes connected electrically to the respective first drain regions; and a first source electrode connected electrically to the first source region; a second trench lateral power MOSFET positioned on the same semiconductor substrate as the first trench lateral power MOSFET, comprising a second gate oxide film and second gate electrodes that are positioned in a second trench; a second source region of a first conductivity type positioned under a bottom surface of the second trench; second drain regions of a first conductivity type positioned on both sides of the second trench; a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions; second drain electrodes connected electrically to the respective second drain regions; and a second source electrode connected electrically to the second source region; a first planar MOSFET positioned on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate; a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode; a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region; and a second planar MOSFET positioned on the same semiconductor substrate as the first trench lateral power MOSFET, comprising a fourth gate oxide film and a fourth gate electrode that are positioned on the surface of the semiconductor substrate; a fourth drain region of a first conductivity type and a fourth source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the fourth gate electrode; a fourth drain electrode connected electrically to the fourth drain region; and a fourth source electrode connected electrically to the fourth source region, the manufacturing method comprising:
forming the first extended drain region and the second extended drain region in the semiconductor substrate;
forming the first trench and the second trench;
forming the first base region and the channel region of the first planar MOSFET simultaneously;
forming the second base region and the channel region of the second planar MOSFET simultaneously;
forming the first gate oxide film, the second gate oxide film, the third gate oxide film, and the fourth gate oxide film;
forming first gate electrodes, second gate electrodes, the third gate electrode, and the fourth gate electrode;
forming first drain regions, the first source region, the third drain region, and the third source region simultaneously;
forming second drain regions, the second source region, the fourth drain region, and the fourth source region simultaneously;
laying an interlayer insulating film over the surface of the semiconductor substrate, and etching the interlayer insulating film to expose the first source region and the second source region at the bottoms of the first trench and the second trench, respectively;
filling the insides of the first trench and the second trench with a first polysilicon layer and a second polysilicon layer that are in contact with the first source region and the second source region, respectively;
laying a passivation film over the surface of the semiconductor substrate, and etching the passivation film and the interlayer insulating film to expose the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, the third source region, the fourth drain region, and the fourth source region; and
laying a metal layer on the passivation film and patterning the metal layer to form first drain electrodes, the first source electrode, second drain electrodes, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode that are in contact with the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, the third source region, the fourth drain region, and the fourth source region, respectively.
55. The manufacturing method according to claim 54, wherein the first polysilicon layer is laid over the surface of the semiconductor substrate after the first gate oxide film, the second gate oxide film, the third gate oxide film, and the fourth gate oxide film have been formed, and then the first polysilicon layer is patterned to form the first gate electrodes, the second gate electrodes, the third gate electrode, and the fourth gate electrode simultaneously.
56. The manufacturing method according to claim 54, wherein the first gate oxide film, the second gate oxide film, and the third gate oxide film, and the fourth gate oxide film are formed simultaneously.
57. The manufacturing method according to claim 54, wherein a body region having a same conductivity type as the first base region is formed under the bottom surface of the first trench after the first trench has been formed and before the first base region and the channel region of the first planar MOSFET are formed.
58. The manufacturing method according to claim 54, wherein a body region having a same conductivity type as the second base region is formed under the bottom surface of the second trench after the second trench has been formed and before the second base region and the channel region of the second planar MOSFET are formed.
59. A manufacturing method of a semiconductor device comprising a first trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a first trench; a first source region of a second conductivity type positioned under a bottom surface of the first trench; first drain regions of a second conductivity type positioned on both sides of the first trench; a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions; first drain electrodes connected electrically to the respective first drain regions; and a first source electrode connected electrically to the first source region; a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and second gate electrodes that are positioned in a second trench; a second source region of a first conductivity type positioned under a bottom surface of the second trench; second drain regions of a first conductivity type positioned on both sides of the second trench; a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions; second drain electrodes connected electrically to the respective second drain regions; and a second source electrode connected electrically to the second source region; a first planar MOSFET positioned on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate; a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode; a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region; and a second planar MOSFET positioned on the semiconductor substrate, comprising a fourth gate oxide film and a fourth gate electrode that are positioned on the surface of the semiconductor substrate; a fourth drain region of a first conductivity type and a fourth source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the fourth gate electrode; a fourth drain electrode connected electrically to the fourth drain region; and a fourth source electrode connected electrically to the fourth source region, the manufacturing method comprising:
forming the first extended drain region and the second extended drain region in a semiconductor substrate;
forming the first trench and the second trench;
forming the first base region and the channel region of the first planar MOSFET simultaneously;
forming the second base region and the channel region of the second planar MOSFET simultaneously;
forming the first gate oxide film, the second gate oxide film, the third gate oxide film, and the fourth gate oxide film;
forming first gate electrodes, second gate electrodes, the third gate electrode, and the fourth gate electrode;
forming first drain regions, the first source region, the third drain region, and the third source region simultaneously;
forming second drain regions, the second source region, the fourth drain region, and the fourth source region simultaneously;
laying an interlayer insulating film over the surface of the semiconductor substrate, and etching the interlayer insulating film to expose the first source region and the second source region at the bottoms of the first trench and the second trench, respectively;
forming, in the first trench and the second trench, a first barrier metal layer and a second barrier metal layer that are in contact with the first source region and the second source region, respectively;
filling the insides of the first trench and the second trench with a first polysilicon layer and a second polysilicon layer that are in contact with the first barrier metal layer and the second barrier metal layer, respectively;
laying a passivation film over the surface of the semiconductor substrate, and etching the passivation film and the interlayer insulating film to expose the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, the third source region, the fourth drain region, and the fourth source region; and
laying a metal layer on the passivation film and patterning the metal layer to form first drain electrodes, the first source electrode, second drain electrodes, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode that are in contact with the first drain regions, the first polysilicon layer, the second drain regions, the second polysilicon layer, the third drain region, the third source region, the fourth drain region, and the fourth source region, respectively.
60. The manufacturing method according to claim 57, including forming body regions having a first conductivity type and then forming extended drain regions having a second conductivity type by double diffusion on both sides of the first trench after the first trench has been formed and before the first base region and the channel region of the first planar MOSFET are formed.
61. The manufacturing method according to claim 58, including forming body regions having a second conductivity type and then forming extended drain regions having a first conductivity type by double diffusion on both sides of the second trench after the second trench has been formed and before the second base region and the channel region of the second planar MOSFET are formed.
62. The semiconductor device according to claim 1, wherein a thickness of the gate oxide film of the at least one trench lateral power MOSFET is thicker than a thickness of the at least one planar MOSFET.
63. The semiconductor device according to claim 17, wherein a thickness of the gate oxide film of the trench lateral power MOSFET is thicker than a thickness of the first and second planar MOSFETs.
64. A semiconductor device positioned on a surface of a semiconductor substrate, comprising:
a gate oxide film and gate electrodes that are positioned in a trench;
a source region positioned under a bottom surface of the trench;
drain regions positioned in a surface layer of the semiconductor substrate on both sides of the trench;
an extended drain region and a base region to serve as channel regions, the extended drain region and the base region being positioned between the source region and the drain regions;
drain electrodes connected electrically to the respective drain regions;
a source electrode connected electrically to the source region;
a plug region positioned under the bottom surface of the trench, for electrically connecting the base region and the source electrode;
a barrier metal layer; and
a conductor that is one of: an n-type or p-type semiconductor extending in the trench from the surface of the semiconductor substrate proximate to the bottom surface of the trench,
wherein the source region is positioned in the base region, and
wherein the source electrode is in contact with the conductor, the conductor is in contact with the barrier metal layer, and the barrier metal layer is in contact with the source region and the plug region.
65. A semiconductor device comprising:
a first trench lateral power MOSFET on a semiconductor substrate, comprising
a first gate oxide film and first gate electrodes that are positioned in a first trench;
a first source region positioned under a bottom surface of the first trench and having a first conductivity type;
first drain regions positioned on both sides of the first trench and having the first conductivity type;
a first extended drain region having the first conductivity type and a first base region having a second conductivity type and to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;
first drain electrodes connected electrically to the respective first drain regions;
a first source electrode connected electrically to the first source region;
a first barrier metal layer; and
a first conductor that is one of an n-type or p-type semiconductor extending in the first trench from the surface of the semiconductor substrate proximate to the bottom surface of the first trench; and
a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising
a second gate oxide film and second gate electrodes that are positioned in a second trench;
a second source region positioned under a bottom surface of the second trench and having the second conductivity type;
second drain regions positioned on both sides of the second trench and having the second conductivity type;
a second extended drain region having the second conductivity type and a second base region having the first conductivity type and to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;
second drain electrodes connected electrically to the respective second drain regions;
a second source electrode connected electrically to the second source region;
a second barrier metal layer; and
a second conductor that is one of: an n-type or p-type semiconductor extending in the second trench from the surface of the semiconductor substrate proximate to the bottom surface of the second trench,
wherein the first source electrode is in contact with the first conductor, the first conductor is in contact with the first barrier metal layer, and the first barrier metal layer is in contact with the first source region, and
wherein the second source electrode is in contact with the second conductor, the second conductor is in contact with the second barrier metal layer, and the second barrier metal layer is in contact with the second source region.