1. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing two or more doped silicon layers over the amorphous silicon layer, each doped silicon layer having at least one characteristic that is different than the other doped silicon layers, wherein depositing the two or more doped silicon layers comprises:
depositing a first doped silicon layer on the amorphous silicon layer under first deposition conditions, wherein the first deposition conditions comprise a deposition rate of between about 800 Angstroms per minute and about 4000 Angstroms per minute, a deposition time of up to about 30 seconds to produce a first doped silicon layer having a resistivity of between about 70 \u03a9cm to about 3000 \u03a9cm; and
depositing a second doped silicon layer on the first doped silicon layer under second deposition conditions different than the first deposition conditions, wherein the second deposition conditions comprise a deposition rate of between about 50 Angstroms per minute and about 800 Angstroms per minute for a deposition time of between about 15 seconds to about 3000 seconds to produce the second doped silicon layer having a resistivity of between about 10 \u03a9cm to about 70 \u03a9cm;
depositing a metal layer over the two or more doped silicon layers;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the two or more doped silicon layers to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
2. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing two or more doped silicon layers over the amorphous silicon layer, each doped silicon layer having at least one characteristic that is different than the other doped silicon layers, wherein depositing the two or more doped silicon layers comprises:
depositing a first doped silicon layer on the amorphous silicon layer under first deposition conditions, wherein the first deposition conditions comprise a deposition rate of between about 1800 Angstroms per minute and about 2200 Angstroms per minute, a deposition time of between about 5 seconds and about 10 seconds to produce a first doped silicon layer having a resistivity of between about 110 \u03a9cm to about 120 \u03a9cm; and
depositing a second doped silicon layer on the first doped silicon layer under second deposition conditions different than the first deposition conditions, wherein, the second deposition conditions comprise a deposition rate of between about 280 Angstroms per minute and about 320 Angstroms per minute for a deposition time of between about 10 seconds to about 18 seconds to produce the second doped silicon layer having a resistivity of between about 30 \u03a9cm to about 40 \u03a9cm;
depositing a metal layer over the two or more doped silicon layers;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the two or more doped silicon layers to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
3. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing two or more doped silicon layers over the amorphous silicon layer, each doped silicon layer having at least one characteristic that is different than the other doped silicon layers, wherein depositing the two or more doped silicon layers comprises:
depositing a first doped silicon layer on the amorphous silicon layer under first deposition conditions; and
depositing a second doped silicon layer on the first doped silicon layer under second deposition conditions different than the first deposition conditions, wherein, the second deposition comprises introducing silane gas at a flow rate of between about 5000 sccm and about 20000 sccm, introducing hydrogen gas at a flow rate of up to about 200000 sccm, introducing 0.5 percent PH3 in H2 at a flow rate of between about 1000 sccm and about 200000 sccm, applying an RF power to a showerhead of between about 500 W and about 15000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils;
depositing a metal layer over the two or more doped silicon layers;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the two or more doped silicon layers to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
4. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing two or more doped silicon layers over the amorphous silicon layer, each doped silicon layer having at least one characteristic that is different than the other doped silicon layers, wherein depositing the two or more doped silicon layers comprises:
depositing a first doped silicon layer on the amorphous silicon layer under first deposition conditions; and
depositing a second doped silicon layer on the first doped silicon layer under second deposition conditions different than the first deposition conditions, wherein the second deposition comprises introducing silane gas at a flow rate of between about 5000 sccm and about 50000 sccm, introducing hydrogen gas at a flow rate of up to about 150000 sccm, introducing 0.5 percent PH3 in H2 at a flow rate of between about 1000 sccm and about 150000 sccm, applying an RF power to a showerhead of between about 10000 W and about 40000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils;
depositing a metal layer over the two or more doped silicon layers;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the two or more doped silicon layers to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
5. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing a first doped silicon layer having a first resistivity on the amorphous silicon layer at a first deposition rate, wherein the first doped silicon layer is deposited under first deposition conditions that comprise a deposition rate of between about 800 Angstroms per minute and about 4000 Angstroms per minute, a deposition time of up to about 30 seconds to produce a first doped silicon layer having a resistivity of between about 70 \u03a9cm to about 300 \u03a9cm;
depositing a second doped silicon layer having a second resistivity less than the first resistivity on the first doped silicon layer, the second doped silicon layer deposited at a second deposition rate less than the first deposition rate, wherein the second doped silicon layer is deposited under second deposition conditions that comprise a deposition rate of between about 50 Angstroms per minute and about 800 Angstroms per minute for a deposition time of between about 15 seconds to about 300 seconds to produce the second doped silicon layer having a resistivity of between about 10 \u03a9cm to about 70 \u03a9cm;
depositing a metal layer over the second doped silicon layer;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the first doped silicon layer and the second doped silicon layer to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
6. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing a first doped silicon layer having a first resistivity on the amorphous silicon layer at a first deposition rate, wherein the first doped silicon layer is deposited under first deposition conditions that comprise a deposition rate of between about 1800 Angstroms per minute and about 2200 Angstroms per minute, a deposition time of between about 5 seconds and about 10 seconds to produce a first doped silicon layer having a resistivity of between about 110 \u03a9cm to about 120 \u03a9cm;
depositing a second doped silicon layer having a second resistivity less than the first resistivity on the first doped silicon layer, the second doped silicon layer deposited at a second deposition rate less than the first deposition rate, wherein the second doped silicon layer is deposited under second deposition conditions that comprise a deposition rate of between about 280 Angstroms per minute and about 320 Angstroms per minute for a deposition time of between about 10 seconds to about 18 seconds to produce the second doped silicon layer having a resistivity of between about 30 \u03a9cm to about 40 \u03a9cm;
depositing a metal layer over the second doped silicon layer;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the first doped silicon layer and the second doped silicon layer to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
7. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing a first doped silicon layer having a first resistivity on the amorphous silicon layer at a first deposition rate;
depositing a second doped silicon layer having a second resistivity less than the first resistivity on the first doped silicon layer, the second doped silicon layer deposited at a second deposition rate less than the first deposition rate, wherein the second doped silicon layer is deposited under deposition conditions that comprise introducing silane gas at a flow rate of between about 5000 sccm and about 20000 sccm, introducing hydrogen gas at a flow rate of up to about 200000 sccm, introducing 0.5 percent PH3 in H2 at a flow rate of between about 1000 sccm and about 200000 sccm, applying an RF power to a showerhead of between about 500 W and about 15000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils;
depositing a metal layer over the second doped silicon layer;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the first doped silicon layer and the second doped silicon layer to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
8. A thin film transistor fabrication method, comprising:
depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;
depositing a first doped silicon layer having a first resistivity on the amorphous silicon layer at a first deposition rate;
depositing a second doped silicon layer having a second resistivity less than the first resistivity on the first doped silicon layer, the second doped silicon layer deposited at a second deposition rate less than the first deposition rate, wherein the second doped silicon layer is deposited under deposition conditions that comprise introducing silane gas at a flow rate of between about 5000 sccm and about 50000 sccm, introducing hydrogen gas at a flow rate of up to about 150000 sccm, introducing 0.5 percent PH3 in H2 at a flow rate of between about 1000 sccm and about 150000 sccm, applying an RF power to a showerhead of between about 10000 W and about 40000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils;
depositing a metal layer over the second doped silicon layer;
patterning the metal layer to form a source electrode and a drain electrode;
patterning the first doped silicon layer and the second doped silicon layer to expose the amorphous silicon layer; and
depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for traffic impact prediction, the system comprising:
a memory having computer readable computer instructions; and
a processor for executing the computer readable instructions to perform a method comprising:
estimating a link level background traffic demand in a transportation network, the estimating the link level background traffic demand including:
receiving information about available routes in the transportation network;
receiving expected background traffic volumes between origins and destinations in the transportation network; and
applying a background traffic flow model that optimizes a background flow of the expected background traffic volumes among the available routes to minimize a sum of background congestion costs, background path entropy, and errors between an observed background traffic flow and the optimized background flow;
identifying alternative routes for at least a subset of the estimated link level background traffic demand, the identifying based on the available routes in the transportation network and event based control plans;
receiving expected additional event based traffic volumes between the origins and the destinations in the transportation network;
estimating a link level total traffic demand in the transportation network based on the expected additional event based traffic volumes, the identified alternative routes, and the estimated link level background traffic demand; and
outputting the estimated link level total traffic demand.
2. The system of claim 1, wherein the observed background traffic flow is received from a subject matter expert (SME).
3. The system of claim 1, wherein the event based control plans include at least one of a variable message sign (VMS), a road closure, a turn restriction, and a detour.
4. The system of claim 1, wherein the identifying alternative routes includes event influenced estimated background traffic being assigned the identified alternative routes based on responsive rerouting.
5. The system of claim 4, wherein input to the responsive rerouting includes input from a SME.
6. The system of claim 1, wherein estimating the link level total traffic demand includes applying a total traffic demand model that optimizes a total flow of the expected background traffic volumes and the expected additional event based traffic volumes among the available routes and the identified alternative routes to minimize a sum of total congestion costs and total path entropy.
7. The system of claim 6, wherein the link level total traffic demand model further minimizes a deviation from the optimized background flow.
8. The system of claim 6 wherein the link level total traffic demand model further minimizes a deviation between observed turning ratios and estimated turning ratios.
9. The system of claim 8, wherein the observed turning ratios are received from a SME.
10. The system of claim 6, wherein the total traffic demand model takes into account spatial-temporal data that is estimated based on a total number of expected event attendees, an event start time, an event end time, and a location and capacity of at least one event parking lot.