1. A method of insert molding an electronic element into a molded product, the molded product being formed by injecting a moldable material into a mold, the method comprising:
adhering the electronic element to a surface of the mold with an adhesive configured to decompose with heat andor pressure in the molding process, wherein the surface to which the electronic element is adhered is free of any features provided for holding the electronic element in place on the mold surface;
injecting the moldable material into the mold such that the moldable material at least partially surrounds the electronic element; and
curing the moldable material, decomposing the adhesive with heat andor pressure to reduce the amount of any residue
wherein the molded product is a doll, and wherein the electronic element includes a controller configured to control an interactive feature incorporated into the doll.
2. The method of claim 1, wherein the electronic element is a printed circuit board.
3. The method of claim 2, wherein the printed circuit board includes circuits formed with surface mount components.
4. The method of claim 1, wherein the adhesive is applied to the electronic element via a release sheet.
5. The method of claim 1, wherein the adhesive is a block copolymer adhesive.
6. The method of claim 1, wherein the adhesive is a pressure-sensitive adhesive.
7. The method of claim 1, wherein the adhesive is applied to the electronic element in a layer having a thickness of 0.002\u20130.005 inches before the electronic element is adhered to the mold.
8. The method of claim 1, wherein injecting the moldable material into the mold includes reaction injection molding with at least two reactive components into the mold.
9. The method of claim 1, wherein the moldable material is selected from the group consisting of ABS plastic and elastomers.
10. The method of claim 1, further comprising removing the molded product from the mold after curing the moldable material, and then coating any remaining adhesive with an inert substance.
11. The method of claim 10, wherein the inert substance is talcum powder.
12. The method of claim 1, wherein the doll is molded via a roto-casting molding process.
13. The method of claim 1, wherein the doll is molded via a slush molding process.
14. The method of claim 1, further comprising adhering a piece of fabric to a surface of the mold before injecting the moldable material into the mold.
15. The method of claim 14, wherein the doll includes a head having an eye, and wherein the piece of fabric is adhered to the mold in a location such that the piece of fabric is insert molded into the head adjacent the eye of the doll’s head.
16. The method of claim 1, further comprising adhering a support piece configured to support a shape of a surface feature of a face of the doll to a surface of the mold before injecting the moldable material into the mold.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a gate electrode formed in a first conductive type region of a silicon semiconductor substrate via an insulator;
a first sidewall formed on a side face of the gate electrode;
a second sidewall formed on a side face of the first sidewall;
a semiconductor layer formed below the second sidewall, including a first impurity layer of a second conductive type and containing germanium, and having substantially the same width as that of the second sidewall;
a second impurity layer formed in a region outside the second sidewall and containing impurities of the second conductive type with a higher concentration than those in the first impurity layer; and
a silicide layer formed on the second impurity layer.
2. The semiconductor device according to claim 1,
wherein a surface of the semiconductor layer is positioned at a higher level than that of a surface of the semiconductor substrate.
3. The semiconductor device according to claim 2,
wherein a surface of the second impurity layer is positioned in a different level from the surface of the semiconductor substrate.
4. The semiconductor device according to claim 1,
wherein a germanium concentration in the second impurity layer is equal to or less than 10%.
5. The semiconductor device according to claim 1,
wherein the semiconductor layer contains silicon germanium.
6. The semiconductor device according to claim 1,
wherein the first conductive type is n-type and the second conductive type is p-type.
7. The semiconductor device according to claim 1,
wherein the second impurity layer has a lower germanium concentration than the semiconductor layer.
8. The semiconductor device according to claim 7,
wherein a surface of the semiconductor layer is positioned at a higher level than that of a surface of the semiconductor substrate.
9. The semiconductor device according to claim 8,
wherein a surface of the second impurity layer is positioned in a different level from the surface of the semiconductor substrate.
10. The semiconductor device according to claim 7,
wherein a germanium concentration in the second impurity layer is equal to or less than 10%.
11. The semiconductor device according to claim 7,
wherein the semiconductor layer contains silicon germanium.
12. The semiconductor device according to claim 1,
wherein the second sidewall has a width greater than the first sidewall.
13. The semiconductor device according to claim 1,
wherein a surface of the semiconductor layer is positioned at a higher level than that of a surface of the semiconductor substrate, a germanium concentration in the second impurity layer is equal to or less than 10%, wherein the semiconductor layer contains silicon germanium, and the first conductive type is n-type and the second conductive type is p-type.
14. A semiconductor device comprising first and second semiconductor elements, wherein:
the first semiconductor element comprising:
a first gate electrode formed in a first conductive type region of a silicon semiconductor substrate via an insulator;
a first sidewall formed on a side face of the first gate electrode;
a second sidewall formed on a side face of the first sidewall;
a semiconductor layer formed below the second sidewall, including a first impurity layer of a second conductive type and containing germanium, and having substantially the same width as that of the second sidewall;
a second impurity layer formed in a region outside the second sidewall and containing impurities of the second conductive type with a higher concentration than those in the first impurity layer; and
a first silicide layer formed on the second impurity layer; and
the second semiconductor element comprising:
a second gate electrode formed in a second conductive type region of the semiconductor substrate via an insulator;
a third sidewall formed on a side face of the second gate electrode;
a fourth sidewall formed on a side face of the third sidewall;
a third impurity layer of a first conductive type formed in the semiconductor substrate below the sidewall of the fourth sidewall;
a fourth impurity layer formed in a region outside the fourth sidewall and containing impurities of a first conductive type with a higher concentration than those in the third impurity layer; and
a second silicide layer formed on the fourth impurity layer.
15. The semiconductor device according to claim 14,
wherein a surface of the semiconductor layer is positioned at a higher level than that of a surface of the semiconductor substrate.
16. The semiconductor device according to claim 14,
wherein a germanium concentration in the second impurity layer is equal to or less than 10%.
17. The semiconductor device according to claim 14,
wherein the semiconductor layer contains silicon germanium.
18. The semiconductor device according to claim 14,
wherein the first conductive type is n-type and the second conductive type is p-type.
19. The semiconductor device according to claim 14,
wherein the second impurity layer has a lower germanium concentration than the semiconductor layer.
20. The semiconductor device according to claim 19,
wherein a surface of the semiconductor layer is positioned at a higher level than that of a surface of the semiconductor substrate.
21. The semiconductor device according to claim 19,
wherein a germanium concentration in the second impurity layer is equal to or less than 10%.
22. The semiconductor device according to claim 19,
wherein the semiconductor layer contains silicon germanium.
23. The semiconductor device according to claim 14,
wherein the second sidewall has a width greater than the first sidewall.
24. The semiconductor device according to claim 14,
wherein a surface of the semiconductor layer is positioned at a higher level than that of a surface of the semiconductor substrate, a germanium concentration in the second impurity layer is equal to or less than 10%, wherein the semiconductor layer contains silicon germanium, and the first conductive type is n-type and the second conductive type is p-type.