1. A semiconductor device structure comprising:
a first region of semiconductor material having a first conductivity type and a first dopant concentration;
a second region of semiconductor material having a second conductivity type, the second region overlying the first region;
a drift region of semiconductor material having the first conductivity type overlying the second region, at least a portion of the second region residing between the first region and the drift region, the drift region having a second dopant concentration; and
a drain region of semiconductor material having the first conductivity type and a third dopant concentration, wherein:
at least a portion of the drift region resides between the second region and the drain region;
the first dopant concentration is less than or equal to the second dopant concentration;
the third dopant concentration is greater than the second dopant concentration; and
the first region is isolated from the drift region.
2. The semiconductor device structure of claim 1, further comprising a layer of dielectric material, wherein the first region overlies the layer of dielectric material.
3. The semiconductor device structure of claim 2, wherein the first region abuts the layer of dielectric material.
4. The semiconductor device structure of claim 1, further comprising a body region of semiconductor material having the second conductivity type, wherein the drift region comprises a lateral drift region that provides a path for current between the drain region and a channel within the body region.
5. The semiconductor device structure of claim 1, wherein a second portion of the second region underlies the drain region and abuts the first region.
6. The semiconductor device structure of claim 5, wherein the second portion of the second region resides laterally between portions of the first region.
7. The semiconductor device structure of claim 6, wherein:
the drift region overlies the portions of the first region; and
the portion of the second region resides vertically between the portions of the first region.
8. The semiconductor device structure of claim 5, wherein the first region circumscribes the second portion.
9. The semiconductor device structure of claim 8, wherein lateral boundaries of the second portion are substantially vertically aligned with lateral boundaries of the drain region.
10. The semiconductor device structure of claim 1, wherein the first region underlies the drain region.
11. The semiconductor device structure of claim 10, wherein the first region and the drain region are vertically aligned.
12. A semiconductor device structure comprising:
a buried region of semiconductor material having a first conductivity type;
a first region of semiconductor material having a second conductivity type overlying the buried region;
a drift region of semiconductor material having the first conductivity type overlying the first region;
a drain region of semiconductor material having the first conductivity type within the drift region, the drain region having a dopant concentration greater than a dopant concentration of the drift region, wherein:
at least a portion of the drift region resides between the drain region and the first region;
at least a portion of the first region resides between the drift region and the buried region; and
the buried region is isolated from the drift region.
13. The semiconductor device structure of claim 12, wherein a dopant concentration of the buried region is less than the dopant concentration of the drift region.
14. The semiconductor device structure of claim 12, further comprising a layer of dielectric material, wherein the buried region overlies and abuts the layer of dielectric material.
15. The semiconductor device structure of claim 14, further comprising a body region of semiconductor material having the second conductivity type, wherein at least a second portion of the first region underlying the body region abuts the layer of dielectric material.
16-20. (canceled)
21. The semiconductor device structure of claim 1, wherein the buried region comprises an annular doped region.
22. The semiconductor device structure of claim 21, wherein the drift region comprises a lateral drift region overlying the annular doped region.
23. The semiconductor device structure of claim 1, further comprising a third region of semiconductor material having the first conductivity type and the first dopant concentration, wherein:
at least a portion of the second region resides between the third region and the lateral drift region;
at least an interior portion of the second region underlying the drain region resides laterally between the first region and the third region; and
a separation distance between interior boundaries of the first region and the third region is greater than or equal to a width of the drain region.
24. The semiconductor device structure of claim 1, wherein the first region is floating.
25. The semiconductor device structure of claim 1, wherein:
a second portion of the second region underlies the drain region
a width of the second portion is greater than or equal to a width of the drain region.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for anti-tachycardia pacing in a heart including a right and left ventricle, comprising:
(a) delivering first anti-tachycardia pacing pulses to the right ventricle; and
(b) delivering second anti-tachycardia pacing pulses to the left ventricle,
wherein the first pacing pulses are delivered simultaneously with the second pacing pulses, and
wherein the first pacing pulses have a polarity that is opposite to a polarity of the second pacing pulses.
2. The method of claim 1, wherein:
step (a) comprises delivering the first anti-tachycardia pacing pulses using a first pair of shorted together electrodes located in the right ventricle; and
step (b) comprises delivering the second anti-tachycardia pacing pulses using a second pair of shorted together electrodes located in the left ventricle.
3. The method of claim 1 wherein the pacing pulses to the left and right ventricles are unipolar pacing pulses.
4. The method of claim 3 wherein the unipolar pacing pulses to the left ventricle are between at least one electrode adjacent the left ventricle and a pulse generator housing.
5. The method of claim 3 wherein the unipolar pacing pulses to the right ventricle are between at least one electrode in the right ventricle and the pulse generator housing.
6. An implantable device for converting a ventricular tachycardia to normal sinus rhythm, comprising:
means for delivering first anti-tachycardia pacing pulses having a first polarity to a right ventricle of a patient’s heart; and
means for delivering second anti-tachycardia pacing pulses to a left ventricle of the heart, the second pacing pulses being delivered simultaneously with the first pacing pulses, and the second pacing pulses having a polarity opposite the first polarity.
7. The device of claim 6, further comprising:
a first pair of electrodes adapted to be implanted in the right ventricle;
a first electrode switch adapted to short together the first pair of electrodes;
a second pair of electrode adapted to be implanted in the left ventricle; and
a second electrode switch adapted to short together the second pair of electrodes,
wherein the means for delivering the first anti-tachycardia pacing pulses to the right ventricle is adapted to deliver the first anti-tachycardia pacing pulses after the first pair of electrodes have been shorted together by the first electrode switch, and
wherein the means for delivering the second anti-tachycardia pacing pulses to the left ventricle is adapted to deliver the second anti-tachycardia pacing pulses after the second pair of electrodes have been shorted together by the second electrode switch.
8. The device of claim 7, wherein the first electrode switch and the second electrode switch are part of an electrode switch bank.
9. The device of claim 6 wherein the implantable device includes a device housing and wherein each of the means for delivering pacing pulses comprises means for delivering unipolar pacing pulses between at least one electrode at a ventricle and the device housing.