1. A fan motor comprising:
a stepping motor for rotating a rotating shaft;
an impeller rotated by the rotating shaft; and
a connecting member for rotatably connecting the impeller relative to the rotating shaft,
wherein the connecting member absorbs an inertia force of the impeller while idly rotating the rotating shaft relative to the impeller in starting the motor and rotating the impeller to follow the rotating shaft as a revolution number of the rotating shaft increases.
2. The fan motor according to claim 1, wherein the connecting member is a coil spring having one end connected to the impeller and the other end fixed to the rotating shaft, the coil spring been wound around the rotating shaft.
3. The fan motor according to claim 1, wherein the stepping motor includes a stator wound with a coil and a rotor having a magnet arranged to be opposed to the stator so that the rotor is rotated by changing a magnetic pole of the stator by energization of the coil
4. The fan motor according to claim 3 further comprising a driving circuit including a CMOS transistor for controlling energization of the coil.
5. The fan motor according to claim 4, wherein the driving circuit is equivalent to an IC of a timepiece.
6. The fan motor according to claim 4, wherein a pulse frequency of the driving circuit output in starting is set to be lower than a pulse frequency in a steady state.
7. The fan motor according to claim 4 further comprising a solar cell provided at a portion of an exterior of the fan motor, wherein the driving circuit is driven by the solar cell as a power source.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a substrate which includes an element region and an isolation region;
a transistor portion which includes a gate insulating film formed on the element region, and a gate electrode having a metal film formed on the gate insulating film and a first semiconductor film formed on the metal film; and
a resistance element portion which includes a second semiconductor film formed above the substrate and formed of the same material as that of the first semiconductor film, and a cavity formed between the substrate and the second semiconductor film.
2. The device according to claim 1,
wherein the resistance element portion further includes a sidewall portion which is formed on the substrate and on a side surface of the second semiconductor film.
3. The device according to claim 2,
wherein the sidewall portion supports the second semiconductor film.
4. The device according to claim 2,
wherein the transistor portion further includes a sidewall portion which is formed on the substrate and on side surfaces of the gate insulating film and the gate electrode, and
the sidewall portion of the resistance element portion and the sidewall portion of the transistor portion are formed of the same material.
5. The device according to claim 1,
wherein a height of the second semiconductor film from an upper surface of the substrate is the same as a height of the first semiconductor film from the upper surface of the substrate.
6. The device according to claim 1,
wherein the second semiconductor film is formed above the isolation region.
7. The device according to claim 1,
wherein the second semiconductor film is formed to cross a boundary between the element region and the isolation region.
8. The device according to claim 1,
wherein each of the first semiconductor film and the second semiconductor film is formed of a silicon film containing an impurity element.
9. The device according to claim 1,
wherein the resistance element portion further includes an insulating film formed on the substrate and formed of the same material as that of the gate insulating film.
10. A manufacturing method of a semiconductor device, comprising:
forming an insulating film on a substrate including an element region and an isolation region;
forming a metal film on the insulating film;
forming a semiconductor film on the metal film;
patterning a stack film including the insulating film, the metal film, and the semiconductor film to form a first stack structure in a transistor forming region and a second stack structure in a resistance element forming region; and
removing the metal film included in the second stack structure to form a cavity between the substrate and the semiconductor film included in the second stack structure.
11. The method according to claim 10, further comprising:
forming a sidewall film which covers a side surface of the second stack structure; and
removing a part of the sidewall film to expose a part of the metal film included in the second stack structure,
wherein the metal film included in the second stack structure is removed by performing etching from the exposed part of the metal film.
12. The method according to claim 10,
wherein removing the metal film included in the second stack structure is performed by a wet etching process.
13. The method according to claim 10,
wherein the second stack structure is formed on the isolation region.
14. The method according to claim 10,
wherein the second stack structure is formed to cross a boundary between the element region and the isolation region.
15. The method according to claim 10,
wherein the semiconductor film is formed of a silicon film containing an impurity element.