1. A method of manufacturing light emitting diode (LED) of a normal structure comprising steps of:
providing a package base having
a top;
a bottom;
a first metal layer being formed on the top of the package base; and
a second metal layer being formed on the bottom of the package base;
providing a light emitting structure comprising
a substrate having a bottom;
a light emitting lamination being formed on the substrate and comprising an n-type semiconductor layer, a light emitting layer, a p-type semiconductor layer and a transparent electrode layer deposited on the substrate in sequence; and
a reflective metal layer being formed on the bottom of the substrate; and
bonding the light emitting structure on the package base with an ultrasonic thermal press technique to connect the first metal layer to the reflective metal layer.
2. The method as claimed in claim 1, wherein each of the first metal layer and the reflective metal layer is composed of the metal that is transferred to low-temperature eutectic phase during thermal pressing.
3. The method as claimed in claim 1, wherein the transparent electrode layer is composed of the material that is selected from the group consisting of indium tin oxide, RuO2, ZnO, NiO and combinations.
4. The method as claimed in claim 1, wherein each of the p-type semiconductor layer, the light emitting layer and the n-type semiconductor layer is composed of GaN, InGaN or AlInGaP.
5. The method as claimed in claim 1, wherein the reflective metal layer is composed of the material that is selected from the group consisting of Al, Ag, Pt, Cr, Mo, W, Au and combinations.
6. The method as claimed in claim 1, wherein the package base is composed of the material that has good thermal conductivity and is selected from the group consisting of silicon, aluminum, copper, wolfram, molybdenum, gallium nitride, aluminum nitride, silicon carbide and combinations.
7. The method as claimed in claim 1, wherein each of the first and the second metal layers on the package base is composed of the material that is selected from the group consisting of Al, Ag, Pt, Cr, Mo, W, Au and combinations.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resistive random access memory, comprising:
a bottom electrode;
an insulating layer disposed on the bottom electrode, wherein the insulating layer has a contact hole having a first width;
a hard mask layer having an opening;
a memory cell, wherein a portion of the memory cell exposed from the opening having a second width, wherein the second width is smaller than the first width; and
a top electrode being coupled with the memory cell.
2. The resistive random access memory according to claim 1, wherein the hard mask is a spacer disposed inside the contact hole.
3. The resistive random access memory according to claim 2, wherein the material of the spacer is silicon oxide.
4. The resistive random access memory according to claim 2, wherein the width of the spacer ranges between 60-100 nm.
5. The resistive random access memory according to claim 2, wherein the second width is substantially equal to the width of the opening.
6. The resistive random access memory according to claim 2, further comprising a conductive layer between the hard mask layer and bottom electrode.
7. The resistive random access memory according to claim 6, wherein the conductive layer is made of tungsten.
8. The resistive random access memory according to claim 1, wherein the bottom electrode is made of tungsten.
9. The resistive random access memory according to claim 1, wherein the hard mask layer is an anti-oxidation barrier.
10. The resistive random access memory according to claim 9, wherein the material of anti-oxidation barrier is nitride.
11. The resistive random access memory according to claim 1, wherein the width of the opening is substantially equal to the second width.
12. A manufacturing method of resistive random access memory, comprising:
(a) forming a bottom electrode;
(b) forming an insulating layer on the bottom electrode, wherein the insulating layer has a contact hole having a first width;
(c) forming a spacer in the contact hole, wherein the spacer has a first opening having a second width smaller than the first width;
(d) forming a memory cell having the second width; and
(e) forming a top electrode coupled with the memory cell.
13. The manufacturing method according to claim 12, further comprising forming an anti-oxidation barrier material between the bottom electrode and the insulating layer.
14. The manufacturing method according to claim 13, further comprising etching the anti-oxidation barrier material so as to form an anti-oxidation barrier having a second opening, wherein the second opening has the second width.
15. The manufacturing method according to claim 14, further comprising removing the spacer.
16. The manufacturing method according to claim 12, wherein between step (b) and step (c), the method further comprises
forming a conductive layer in the contact hole;
planarizing the conductive layer to expose the insulating layer; and
etching the conductive layer for creating a distance between the surface of the conductive layer and the surface of the insulating layer.
17. The manufacturing method according to claim 16 further comprising oxidizing the conductive layer prior to step (c).
18. The manufacturing method according to claim 16, wherein the step (d) further comprises oxidizing the conductive layer
19. The manufacturing method according to claim 12, further comprising oxidizing the bottom electrode prior to the step (c).
20. The manufacturing method according to claim 12, wherein the step (d) further comprises oxidizing the bottom electrode so as to form an oxide layer.