1. A method for inspecting a silicon wafer comprising the step of, when inspecting the silicon wafer, inspecting a defect having the entire defect size of 0.5 m or more in which microdefects gather in a colony state.
2. A method for inspecting a silicon wafer according to claim 1, wherein the defect is inspected with a laser microscope based on a confocal optical system or a dark field microscope.
3. A method for manufacturing a silicon wafer comprising the steps of polishing the silicon wafer;
cleaning and drying the polished silicon wafer; and
inspecting a defect having the entire defect size of 0.5 m or more in which microdefects gather in a colony state with a laser microscope based on a confocal optical system or a dark field microscope after the cleaning and drying step.
4. A method for manufacturing a silicon wafer comprising the steps of:
mirror polishing the silicon wafer;
cleaning and drying the mirror polished silicon wafer; and
preventing deposition of impurities on a surface of the wafer and also generation of a defect having the entire defect size of 0.5 m or more in which microdefects gather in a colony state after the wafer is mirror polished.
5. A method of fabricating a semiconductor device comprising the steps of:
inspecting a defect having the entire defect size of 0.5 m or more in which microdefects gather in a colony state in a silicon wafer;
selecting the silicon wafer not having the defect; and
fabricating the semiconductor device by using the silicon wafer not having the defect.
6. A silicon wafer which is mirror polished and has no defect having the entire defect size of 0.5 m or more in which microdefects gather in a colony state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film,
wherein the semiconductor substrate has been subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si, after forming the gate electrode,
wherein the gate electrode includes an SiGe layer and a polycrystal silicon layer formed at a layer upward therefrom, and
wherein a side etching amount at two side faces of the gate electrode is equal to or smaller than 40% of a length in a channel length direction of the polycrystal silicon layer constituting the gate electrode.
2. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film,
wherein the semiconductor substrate has been subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si,
wherein the gate electrode includes an SiGe layer and a polycrystal silicon layer formed at a layer upward therefrom, and
wherein a length in a channel length direction of the gate electrode at the SiGe layer, is equal to a length in the channel length direction of the polycrystal silicon layer constituting the gate electrode.
3. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film,
wherein the semiconductor substrate has been subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si, after forming the gate electrode,
wherein the gate electrode includes an SiGe layer and a metal layer formed at a layer upward therefrom, and
wherein a side etching amount at two sides faces of the gate electrode is equal to or smaller than 40% of a length in a channel length direction of the metal layer constituting the gate electrode.
4. A semiconductor integrated circuit device comprising:
(a) a gate insulating film formed over a main face of a semiconductor substrate; and
(b) a gate electrode formed over the gate insulating film,
wherein the semiconductor substrate has been subjected to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si, after forming the gate electrode, and
wherein a length in a channel length direction of the gate electrode at an SiGe layer, is equal to a length in the channel length direction of a metal layer constituting the gate electrode.