What is claimed is:
1. A strain compensation amplifier comprising: a strain detection circuit in which an input signal is distributed by a power distributor, and a signal obtained by amplifying one output by a main amplifier via a first variable attenuator and a first variable phase unit is synthesized with a signal obtained by adjusting a timing of another output distributed from said power distributor by a first delay unit by a first power synthesizer to detect a strain component generated in said main amplifier; and a strain removal circuit in which a signal obtained by amplifying said strain component outputted from said first power synthesizer by an auxiliary amplifier via a second variable attenuator and a second variable phase unit is reverse-phase synthesized with a signal obtained by adjusting a timing of a signal outputted from said first power synthesizer and amplified by the main amplifier by a second delay unit by a second power synthesizer to offset said strain component, a monitor output is obtained by a directional coupler, and a unidirectional property is enhanced by an isolator to obtain a power synthesis output, wherein at least two or more of said power distributor, said first delay unit, said first power synthesizer, said second delay unit, said second power synthesizer, said directional coupler, said isolator, a terminating resistor of said second power synthesizer, and the terminating resistor of said directional coupler are unified.
2. The strain compensation amplifier according to claim 1 wherein said power distributor and said first delay unit are unified.
3. The strain compensation amplifier according to claim 1 wherein said first delay unit and said first power synthesizer are unified.
4. The strain compensation amplifier according to claim 1 wherein said first power synthesizer and said second delay unit are unified.
5. The strain compensation amplifier according to claim 1 wherein said second delay unit and said second power synthesizer are unified.
6. The strain compensation amplifier according to claim 1 wherein said second power synthesizer and said directional coupler are unified.
7. The strain compensation amplifier according to claim 1 wherein said directional coupler and said isolator are unified.
8. The strain compensation amplifier according to claim 1 wherein said power distributor, said first delay unit and said first power synthesizer are unified.
9. The strain compensation amplifier according to claim 1 wherein said first delay unit, said first power synthesizer and said second delay unit are unified.
10. The strain compensation amplifier according to claim 1 wherein said first power synthesizer, said second delay unit and said second power synthesizer are unified.
11. The strain compensation amplifier according to claim 1 wherein said second delay unit, said second power synthesizer and said directional coupler are unified.
12. The strain compensation amplifier according to claim 1 wherein said second power synthesizer, said directional coupler and said isolator are unified.
13. The strain compensation amplifier according to claim 1 wherein said power distributor, said first delay unit, said first power synthesizer and said second delay unit are unified.
14. The strain compensation amplifier according to claim 1 wherein said first delay unit, said first power synthesizer, said second delay unit and said second power synthesizer are unified.
15. The strain compensation amplifier according to claim 1 wherein said first power synthesizer, said second delay unit, said second power synthesizer and said directional coupler are unified.
16. The strain compensation amplifier according to claim 1 wherein said second delay unit, said second power synthesizer, said directional coupler and said isolator are unified.
17. The strain compensation amplifier according to claim 1 wherein said power distributor, said first delay unit, said first power synthesizer, said second delay unit and said second power synthesizer are unified.
18. The strain compensation amplifier according to claim 1 wherein said first delay unit, said first power synthesizer, said second delay unit, said second power synthesizer and said directional coupler are unified.
19. The strain compensation amplifier according to claim 1 wherein said first power synthesizer, said second delay unit, said second power synthesizer, said directional coupler and said isolator are unified.
20. The strain compensation amplifier according to claim 1 wherein said power distributor, said first delay unit, said first power synthesizer, said second delay unit, said second power synthesizer and said directional coupler are unified.
21. The strain compensation amplifier according to claim 1 wherein said first delay unit, said first power synthesizer, said second delay unit, said second power synthesizer, said directional coupler and said isolator are unified.
22. The strain compensation amplifier according to claim 1 wherein said power distributor, said first delay unit, said first power synthesizer, said second delay unit, said second power synthesizer, said directional coupler and said isolator are unified.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A differential circuit to read differential data from a disk by a current bias on a plurality of read heads, comprising:
a read circuit to read said differential data from said disk by maintaining said current bias on said read head by maintaining a safe current; and
wherein said safe current is below a maximum current of all said plurality of read heads.
2. A differential circuit, as in claim 1, wherein said safe voltage is maintained across a capacitor of said read circuit.
3. A differential circuit, as in claim 1, wherein a head switching time of said read circuit is a less than 500 ns.
4. A disk system to read information from a disk, comprising:
a readwrite head to read and write information from said disk;
a read channel to process said information; and
a differential circuit to read differential data from a disk by a current bias on a plurality of read heads during servo write module, comprising:
a read circuit to read said differential data from said disk by maintaining said current bias on said read head by maintaining a safe current; and
wherein said safe current is below a maximum current of all said plurality of read heads in frequency.
5. A disk system as in claim 4, wherein said safe voltage is maintained across a capacitor of said read circuit.
6. A disk system as in claim 4, wherein said a switching time of said read circuit is a less than 500 ns.