1. A semiconductor memory having an operation mode externally settable, the memory comprising:
a plurality of registers for holding operation mode information for the semiconductor memory;
a register control circuit for updating the operation mode information for each of the plurality of registers on a time division basis at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order;
a command generation section for generating the write commands, the read commands, or a test start command by which write operation or read operation does not occur in response to a control signal externally inputted and for regenerating the test start command every update of the plurality of registers; and
a data pad compression circuit for changing the operation mode information to be written to the plurality of registers by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.
2. The semiconductor memory according to claim 1, wherein when the test start command is generated, a clock signal is stopped to be inputted to the command generation section.
3. The semiconductor memory according to claim 1, wherein the operation mode information is partial size, burst length, or read latency of the semiconductor memory.
4. A semiconductor memory having an operation mode externally settable, the memory comprising:
a plurality of registers for holding operation mode information for the semiconductor memory;
a command generation section for generating a test start command in response to a control signal externally inputted;
a data pad compression circuit for generating the operation mode information to be written to the plurality of registers by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent;
a mask control circuit for generating a mask signal by which only updating of the operation mode information in an unupdated register out of the plurality of registers is permitted and the updating of the operation mode information in remaining registers out of the plurality of registers is skipped, at the time of updating the operation mode information; and
a register control circuit for performing an update process in which the updating of the operation mode information in the remaining registers designated by the mask signal is skipped and the operation mode information generated according to the code is written to the unupdated register permitted by the mask signal, at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order,
wherein:
the command generation section generates the test start command again if there is an unupdated register out of the plurality of registers after the update-process;
the data pad compression circuit inputs another code and changes the operation mode information; and
the register control circuit performs the update process by using the operation mode information changed.
5. The semiconductor memory according to claim 4, wherein the operation mode information is partial size, burst length, or read latency of the semiconductor memory.
6. A semiconductor memory having an operation mode externally settable, the memory comprising:
a plurality of registers for holding operation mode information for the semiconductor memory;
a storage section for inputting and storing in advance operation mode information for update or codes for changing operation mode information as many as a number of the plurality of registers; and
a register control circuit for beginning an update process for updating the operation mode information for each of the plurality of registers on a time division basis at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order and for writing the corresponding operation mode information for update or operation mode information generated according to the codes to the plurality of registers.
7. The semiconductor memory according to claim 6, further comprising a data pad compression circuit for generating the operation mode information to be set in the plurality of registers at the time of updating the plurality of registers by inputting the corresponding codes and by using test data inputted to part of data pads, after inverting the test data or in its original condition according to the corresponding codes, as data for a rest of the data pads.
8. The semiconductor memory according to claim 6, wherein the operation mode information are partial size, burst length, or read latency of the semiconductor memory.
9. A method for testing a semiconductor memory having an operation mode externally settable, the method comprising the steps of:
generating a test start command by which write operation or read operation does not occur, in response to a control signal from an outside of the semiconductor memory;
generating operation mode information by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent;
writing the operation mode information generated according to a code to each of a plurality of registers on a time division basis at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order; and
regenerating the test start command and generating operation mode information to be set in a register to be updated next out of the plurality of registers by inputting another code, every update of the operation mode information in the plurality of registers.
10. The method according to claim 9, wherein when the test start command is generated, a clock signal is stopped.
11. The method according to claim 9, wherein the operation mode information is partial size, burst length, or read latency of the semiconductor memory.
12. A method for testing a semiconductor memory having an operation mode externally settable, the method comprising the steps of:
generating a test start command in response to a control signal from an outside of the semiconductor memory;
generating operation mode information by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent;
generating a mask signal by which only updating of the operation mode information in an unupdated register out of the plurality of registers is permitted and the updating of the operation mode information in remaining registers out of the plurality of registers is skipped, at the time of updating the operation mode information held in the plurality of registers;
performing an update process in which the updating of the operation mode information in the remaining registers designated by the mask signal is skipped and the operation mode information generated according to the code is written to the unupdated register permitted by the mask signal, at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order; and
generating the test start command again in a case where there is an unupdated register out of the plurality of registers after the update process, inputting another code and changing the operation mode information, and performing the update process by using the operation mode information changed.
13. The method according to claim 12, wherein the operation mode information is partial size, burst length, or read latency of the semiconductor memory.
14. A method for testing a semiconductor memory having an operation mode externally settable, the method comprising the steps of:
inputting and storing operation mode information for update or codes for changing operation mode information as many as a number of a plurality of registers for holding the operation mode information;
beginning an update process for updating the operation mode information for each of the plurality of registers on a time division basis at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order; and
writing the corresponding operation mode information for update or operation mode information generated according to the codes to the plurality of registers at the time of updating the plurality of registers.
15. The method according to claim 14, wherein a data pad compression circuit generates the operation mode information to be set in the plurality of registers at the time of updating the plurality of registers by inputting the corresponding codes and by using test data inputted to part of data pads, after inverting the test data or in its original condition according to the corresponding codes, as data for a rest of the data pads.
16. The method according to claim 14, wherein the operation mode information are partial size, burst length, or read latency of the semiconductor memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
I claim as my invention:
1. A universal pan lid absorbing and filtering steam and smell, comprising a pan covering flat and a holding-knob, characterized in that a filtering and purifying filter is housed in a chamber made inside the knob in communication with a central opening made in the flat in a position corresponding to the knob.
2. The lid according to claim 1, characterized in that the knob comprises a box like body consisting of a lower half shell applied to the lid flat and a removable upper half shell to gain access to the filter chamber.
3. The lid according to claim 2, characterized in that a battery operated sucking fan is also housed inside the knob.
4. The lid according to claim 2, characterized in that the lower half shell is provided with an annular sucker for its application on the flat opening.
5. The lid according to claim 2, characterized in that the knob upper half shell has an ergonomic shape allowing to grasp the lid without contact with the outgoing hot steam and is made of shock resistant anti-slip material.
6. The lid according to claim 1, characterized in that the filter is provided with activated charcoal with a high absorbing and filtering power.
7. The lid according to claim 1, characterized in that the filter comprises two layers of filtering cloth between which granules of activated charcoal are embedded.
8. The lid according to claim 6, characterized in that the filter changes color when its saturation is reached allowing its timely replacement.
9. The lid according to claim 6, characterized in that the activated charcoal is made of coconut material.
10. The lid according to claim 1, characterized in that the lid flat is made of fire-resistant tempered glass.
11. The lid according to claim 1, characterized in that the lid flat is transparent for a cooking visual control.
12. The lid according to claim 1, characterized in that the flat has an opening with a tight sealing closure, for introduction of tools and addition of ingredients to the food to be cooked.
13. The lid according to claim 1, characterized in that the flat is made of food compatible metal.
14. The lid according to claim 1, characterized in that the flat is plain of a size fitting to a corresponding diameter of pan or pot.
15. The lid according to claim 1, characterized in that the flat is stepped, having a set of concentric steps, each corresponding to a size of pot or pan thus being applicable on pots or pans of any normally used size.