1. A chip, comprising:
a latch comprising
a storage circuit to store data and having an enable node to enable data to be written into the storage circuit; and
an enable circuit coupled to the enable node to assert the enable node in response to a clock assertion, the enable circuit having a hold component to hold the enable node asserted after the clock de-asserts and a release component to release the enable node from its assertion in response to data written into the storage circuit, wherein the storage circuit has complementary state outputs to indicate the stored data and wherein the release component comprises first and second transistors coupled to the enable node and having control inputs coupled to the complementary state outputs to release the enable node when data is written to the storage circuit.
2. The chip of claim 1, in which the storage circuit comprises first and second cross-coupled inverters to provide the complementary state outputs.
3. The chip of claim 1, in which the first and second transistors comprise N-type field effect transistors coupled between the enable node and a low supply reference to discharge the enable node when the data is written into it.
4. The chip of claim 3, in which the first transistor has a gate coupled to a first one of the complementary state outputs.
5. The chip of claim 4, in which the second transistor has a gate coupled to a second one of the complementary state outputs.
6. The chip of claim 3, in which the first and second N-type transistors are coupled between the enable node and a third transistor that is coupled to the low supply reference.
7. The chip of claim 1, in which the holder component comprises a transistor coupled between the enable node and a high supply reference.
8. A computer system, comprising:
a processor having first and second clock domains and a synchronization latch in said second clock domain to synchronize data coming from the first clock domain, the synchronization latch having:
complementary state outputs and
an enable node to writably enable the complementary state outputs, the processor having an enable circuit coupled to the enable node to assert the enable node in response to a clock assertion, the enable circuit having a hold component to hold the enable node asserted after the clock de-asserts and a release component to release the enable node from its assertion in response to data being written into the complementary state outputs, wherein the release component comprises first and second transistors coupled to the enable node and having control inputs coupled to the complementary state outputs to release the enable node when data is written to the synchronization latch.
9. The computer system of claim 8, in which the synchronization latch comprises first and second cross-coupled inverters to provide the complementary state outputs.
10. The system of claim 8, in which the first and second transistors comprise N-type field effect transistors coupled between the enable node and a low supply reference to discharge the enable node when the data is written into it.
11. The system of claim 10, in which the first transistor has a gate coupled to a first one of the complementary state outputs.
12. The system of claim 11, in which the second transistor has a gate coupled to a second one of the complementary state outputs.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for preserving design intent of a Non-Uniform Rational B-spline (NURBS) surface without representation of a parent surface, comprising:
representing an output surface having control points that are independent from a refinement of said output surface, the output surface c defined by
c
\u2061
(
u
,
v
)
=
\u2211
i
=
0
I
–
1
\u2062
\u2062
\u2211
j
=
0
J
–
1
\u2062
\u2062
c
i
,
j
\u2062
N
m
,
i
,
u
\u2061
(
u
)
\u2062
N
n
,
j
,
v
\u2061
(
v
)
;
interpolating a base surface from said output surface, the base surface b defined by
b
\u2061
(
u
,
v
)
=
\u2211
k
=
0
K
–
1
\u2062
\u2062
\u2211
l
=
0
L
–
1
\u2062
\u2062
b
k
,
l
\u2062
N
r
,
k
,
p
\u2061
(
u
)
\u2062
N
s
,
t
,
q
\u2061
(
v
)
;
calculating a delta vector that is a difference between said output surface and said base surface; and
transforming said delta vector based upon a local coordinate system of a normal vector and a tangent plane of said base surface to form a delta surface, wherein r>1, s>1, m>1, and n>1 are orders, p={pk}k=0K+r\u22121 and q={ql}l=0L+s\u22121 are knot sequences of b in a u-direction and a v-direction, respectively, Nr,k,p denotes the kth normalized B-spline of order r with respect to a knot sequence p, Ns,l,q denotes the k1th normalized B-spline of order s with respect to a knot sequence q, bk,l\u03b53 denotes a (k,l)th control point, u={ui}i=0l+m\u22121 and v={vj}j=0j+s\u22121 are knot sequences of b in a u-direction and a v-direction, respectively.
2. The method of claim 1, wherein said output surface is a NURBS surface.
3. The method of claim 1, wherein said refinement is a degree elevation.
4. The method of claim 1, wherein said refinement is a knot sequence.
5. The method of claim 1, wherein said interpolating of said base surface occurs at a Greville abscissae.
6. The method of claim 1, wherein said normal vector and said tangent plane are first partial derivatives.
7. The method of claim 1, wherein said transforming of said base surface occurs at an associated Greville abscissa.
8. The method of claim 1 further comprising:
generating a new output surface from a new base surface using the delta surface.
9. The method of claim 8, wherein the output surface is the NURBS surface, and wherein generating the new output surface comprises:
preserving the design intent of the NURBS surface in the new output surface by generating the new output surface from the new base surface using the transformed delta vector.
10. The method of claim 8, wherein the new surface is generated using the output surface without receipt of the parent surface and wherein the parent surface is an original surface modified to form the output surface.
11. A system for preserving design intent of a Non-Uniform Rational B-spline (NURBS) surface without representation of a parent surface, comprising:
a computer system, wherein said computer system includes a memory, a processor, a user input device, and a display device;
a computer generated geometric model stored in said memory of said computer system, wherein the geometric model is in a computer-aided design (CAD) format; and
wherein the computer system is configured to:
represent an output surface having control points that are independent from a refinement of said output surface, the output surface c defined by
c
\u2061
(
u
,
v
)
=
\u2211
i
=
0
I
–
1
\u2062
\u2062
\u2211
j
=
0
J
–
1
\u2062
\u2062
c
i
,
j
\u2062
N
m
,
i
,
u
\u2061
(
u
)
\u2062
N
n
,
j
,
v
\u2061
(
v
)
,
interpolate a base surface from said output surface, the base surface b defined by
b
\u2061
(
u
,
v
)
=
\u2211
k
=
0
K
–
1
\u2062
\u2062
\u2211
l
=
0
L
–
1
\u2062
\u2062
b
k
,
l
\u2062
N
r
,
k
,
p
\u2061
(
u
)
\u2062
N
s
,
t
,
q
\u2061
(
v
)
,
calculate a delta vector that is a difference between said output surface and said base surface, and
transform said delta vector based upon a local coordinate system of a normal vector and a tangent plane of said base surface to form a delta surface, wherein r>1, s>1, m>1, and n>1 are orders, p={pk}k=0k+r\u22121 and q={ql}l=0L+s\u22121 are knot sequences of b in a u-direction and a v-direction, respectively, Nr,k,p denotes the kth normalized B-spline of order r with respect to a knot sequence p, Ns,l,q denotes the 1th normalized B-spline of order s with respect to a knot sequence q, bk,l\u03b53 denotes a (k,l)th control point, u={ui}i=0 l+m\u22121 and v={vj}j=0J+s\u22121 are knot sequences of b in a u-direction and a v-direction, respectively.
12. The system of claim 11, wherein said output surface is a NURBS surface.
13. The system of claim 11, wherein said refinement is a degree elevation.
14. The system of claim 11, wherein said refinement is a knot sequence.
15. The system of claim 11, wherein said interpolating of said base surface occurs at a Greville abscissae.
16. The system of claim 11, wherein said normal vector and said tangent plane are first partial derivatives.
17. The system of claim 11, wherein said transforming of said base surface occurs at an associated Greville abscissa.
18. A data processing system for preserving design intent of a Non-Uniform Rational B-spline (NURBS) surface without representation of a parent surface, comprising:
a storage device storing program code; and
a processor operably connected to the storage device, the processor configured to execute the program code to:
represent an output surface having control points that are independent from a refinement of said output surface, the output surface c defined by
c
\u2061
(
u
,
v
)
=
\u2211
i
=
0
I
–
1
\u2062
\u2062
\u2211
j
=
0
J
–
1
\u2062
\u2062
c
i
,
j
\u2062
N
m
,
i
,
u
\u2061
(
u
)
\u2062
N
n
,
j
,
v
\u2061
(
v
)
;
interpolate a base surface from said output surface, the base surface b defined by
b
\u2061
(
u
,
v
)
=
\u2211
k
=
0
K
–
1
\u2062
\u2062
\u2211
l
=
0
L
–
1
\u2062
\u2062
b
k
,
l
\u2062
N
r
,
k
,
p
\u2061
(
u
)
\u2062
N
s
,
t
,
q
\u2061
(
v
)
;
calculate a delta vector that is a difference between said output surface and said base surface; and
transform said delta vector based upon a local coordinate system of a normal vector and a tangent plane of said base surface to form a delta surface, wherein r>1, s>1, m>1, and n>1 are orders, p={pk}k=0K+r\u22121 and q={ql}l=0L+s\u22121 are knot sequences of b in a u-direction and a v-direction, respectively, Nr,k,p denotes the kth normalized B-spline of order r with respect to a knot sequence p, Ns,l,q denotes the 1th normalized B-spline of order s with respect to a knot sequence q, bk,l\u03b53 denotes a (k,1)th control point, u={ui}i=0l+m\u22121 and v={vj}j=0J+s\u22121 are knot sequences of b in a u-direction and a v-direction, respectively.
19. A system for preserving design intent of a Non-Uniform Rational B-spline (NURBS) surface without representation of a parent surface, comprising:
a computer system, wherein said computer system includes a memory, a processor, a user input device, and a display device;
a computer generated geometric model stored in said memory of said computer system, wherein the geometric model is in a computer-aided design (CAD) format; and
wherein the computer system is configured to identify the NURBS surface, wherein the NURBS surface is a child surface formed from modification of the parent surface in accordance with the design intent, modify coordinates of said child surface independent from said parent surface to form a modified child surface, and preserve said design intent of the NURBS surface using the modified child surface.