1. A miniature monopole antenna for dual-frequency printed circuit board, comprising:
a dielectric printed wire board;
a printed wire, being printed on one side of said dielectric printed wire board and one of its ends serving as a signal feed terminal;
a metal grounding surface, being printed on another side of said dielectric printed wire board at a position corresponding to said printed wire;
two radiators, of which one being extended from one end of said printed wire at a position other than the corresponding metal grounding surface, and being bent into approximately 90 degrees after being extended to a predetermined length in the direction away from the metal grounding surface to form a radiator of the predetermined length, and then extended along the direction parallel to said radiator and bent into approximately 90 degrees and being extended to another predetermined length along the direction parallel to said radiator and bent to approximately 90 degrees and then being extended to a corresponding position on another end of said printed wire to define another radiator.
2. The miniature monopole antenna for dual-frequency printed circuit board of claim 1, wherein said two radiators are substantially equal in length.
3. The miniature monopole antenna for dual-frequency printed circuit board of claim 1, wherein said two radiators are parallel to each other, and maintain a predetermined distance apart, and said distance is not larger than 1.5 times of the width of the printed wire and not less than 0.5 times of the width of the printed wire.
4. The miniature monopole antenna for dual-frequency printed circuit board of claim 1, wherein said metal grounding surface keeps its edge along the direction horizontal to said radiators and an appropriate distance between the bending position where said two radiators being connected, and said distance falls in the range of 40%-60% of the length of said each radiator.
5. The miniature monopole antenna for dual-frequency printed circuit board of claim 1, wherein said radiator proximate said metal grounding surface keeps its external edge at a predetermined distance from the corresponding edge of said metal grounding surface, and the range of said distance is not larger than 5.5 times of the width W of said printed wire and not less than 2 times of the width W of said printed wire.
6. The miniature monopole antenna for dual-frequency printed circuit board of claims 1, wherein said monopole antenna has a length extending from the printed wire at a position other than the metal grounding surface to the free end of another radiator through the radiator approximately equal to one quarter of the desired dual-frequency highlow resonance wavelength.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit (IC) comprising:
trace logic for operably coupling to at least one memory element and for providing trace information for a signal processing system, the trace logic comprising:
trigger detection logic for detecting at least one trace trigger;
memory access logic arranged to perform, upon detection of the at least one trace trigger, at least one read operation for at least one memory location of the at least one memory element associated with the at least one detected trigger;
memory content message generation logic arranged to generate at least one memory content message comprising information relating to a result of the at least one read operation performed by the memory access logic; and
output logic for outputting the at least one memory content message.
2. The integrated circuit of claim 1 wherein the trigger detection logic is arranged, upon detection of the at least one trace trigger, to generate at least one trace trigger message for outputting by the output logic.
3. The integrated circuit of claim 2 wherein the trace logic further comprises message queuing logic for queuing memory content messages and trace trigger messages to be output by output logic.
4. The integrated circuit of claim 1 wherein the trigger detection logic is operably coupled to a virtual bus of the signal processing system, and is arranged to trace changes of program flow andor data accesses on the virtual bus between a system core element and a cache memory element.
5. The integrated circuit of claim 1 wherein at least one of a memory address and a memory size with which the at least one detected trigger is associated, and for which the at least one read operation is performed by the memory access logic, are configurable.
6. The integrated circuit of claim 1 wherein the memory access logic comprises direct memory access (DMA) logic operably coupled to the at least one memory element of the signal processing system.
7. The integrated circuit of claim 1 wherein the output logic is arranged to output the at least one memory content message to at least one from a group of:
a trace port;
a virtual trace buffer within the at least one memory element; and
a dedicated trace buffer.
8. The Integrated circuit of claim 1 wherein the at least one trace trigger comprises at least one from a group of:
a change of process flow;
a specific data access;
a process address;
a data address.
9. The Integrated circuit of claim 1 wherein the trace logic comprises a hardware trace module.
10. The Integrated circuit of claim 1 wherein the trace logic is operably coupled to a trace port and at least one from the following group is arranged to be configurable via the trace port;
at least one trace trigger to be detected by trigger detection logic;
at least one memory address associated with the at least one trace trigger;
at least one memory size associated with the at least one trace trigger.
11. A method for providing trace information for a signal processing system, the method comprising:
detecting at least one trace trigger;
upon detection of the at least on trace trigger, performing at least one read operation for at least one memory location associated with the at least one detected trigger;
generating at least one memory content message comprising information relating to a result of the at least one read operation; and
outputting the at least one memory content message.
12. The integrated circuit of claim 2 wherein the trigger detection logic is operably coupled to a virtual bus of the signal processing system, and is arranged to trace changes of program flow andor data accesses on the virtual bus between a system core element and a cache memory element.
13. The integrated circuit of claim 3 wherein the trigger detection logic is operably coupled to a virtual bus of the signal processing system, and is arranged to trace changes of program flow andor data accesses on the virtual bus between a system core element and a cache memory element.
14. The integrated circuit of claim 2 wherein at least one of a memory address and a memory size with which the at least one detected trigger is associated, and for which the at least one read operation is performed by the memory access logic, are configurable.
15. The integrated circuit of claim 3 wherein at least one of a memory address and a memory size with which the at least one detected trigger is associated, and for which the at least one read operation is performed by the memory access logic, are configurable.
16. The integrated circuit of claim 4 wherein at least one of a memory address and a memory size with which the at least one detected trigger is associated, and for which the at least one read operation is performed by the memory access logic, are configurable.
17. The integrated circuit of claim 2 wherein the memory access logic comprises direct memory access (DMA) logic operably coupled to the at least one memory element of the signal processing system.
18. The integrated circuit of claim 3 wherein the memory access logic comprises direct memory access (DMA) logic operably coupled to the at least one memory element of the signal processing system.
19. The integrated circuit of claim 4 wherein the memory access logic comprises direct memory access (DMA) logic operably coupled to the at least one memory element of the signal processing system.
20. The integrated circuit of claim 5 wherein the memory access logic comprises direct memory access (DMA) logic operably coupled to the at least one memory element of the signal processing system.