1. A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising:
forming source and drain regions in a semiconductor substrate; and
forming a gate stack on the semiconductor substrate by steps including:
depositing a thin oxide layer onto the semiconductor substrate;
depositing a silicon layer onto said thin oxide layer to form a floating gate region of the memory cell, the floating gate region including an entire top surface;
directly nitriding the entire top surface of said floating gate region, thereby forming a barrier layer of silicon nitride oxide on the entire top surface of the floating gate region;
depositing a dielectric layer directly on the barrier layer formed by directly nitriding the entire top surface of the floating gate region such that no portion of the dielectric layer contacts the silicon layer; and
forming a conductive layer on the dielectric layer;
wherein a nitrogen distribution inside the silicon nitride oxide layer, formed by direct nitridation, is no less than 1e22 atcm3 as peak value, for a total amount of no less than 1e15 atcm3.
2. A process according to claim 1, wherein the thickness of the silicon nitride oxide layer, formed by direct nitridation, varies between 0.5 to 5.0 nm.
3. A process according to claim 1, wherein the dielectric layer is etched, on either batch or single wafers systems, subsequently to said direct nitridation step.
4. A process according to claim 1, further comprising dry etching the silicon layer to define the floating gate region of the cell immediately before said direct nitridation step.
5. A process according to claim 1, further comprising masking and dry etching the silicon layer to define the floating gate region of the cell immediately after the direct nitridation step.
6. A process according to claim 1, wherein the dielectric layer includes a triple ONO layer formed by CVD.
7. A process according to claim 6, wherein an overall thickness of the silicon nitride oxide layer and the triple ONO layer, is equal to or less than 130 Angstroms.
8. A process according to claim 6, further comprising densifying said triple ONO layer by heat treatment under an N2, H2O and O2 atmosphere.
9. A process according to claim 1, wherein the dielectric layer includes a single layer of silicon oxide formed by CVD.
10. A process according to claim 9, wherein an overall electrical thickness of the silicon nitride oxide layer and the single layer of silicon oxide is equal to or less than 130 Angstroms.
11. A process according to claim 9, further comprising densifying said single layer of silicon oxide by heat treatment under an N2, H2O and O2 atmosphere.
12. A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising:
forming source and drain regions in a semiconductor substrate; and
forming a gate stack on the semiconductor substrate by steps including:
forming a thin dielectric layer on the semiconductor substrate;
forming a first conductive layer on said thin dielectric layer, the first conductive layer forming a floating gate region having an entire top surface;
directly nitriding an entire top surface of the floating gate region, using radical nitrogen, thereby forming a barrier layer on the entire top surface of the floating gate region;
forming an interlevel dielectric layer directly on the barrier layer, whereby the barrier layer intervenes between the interlevel dielectric layer and the floating gate region such that no portion of the floating gate region contacts the interlevel dielectric layer; and
forming a second conductive layer on the interlevel dielectric layer, wherein the barrier layer includes silicon nitride oxide having a nitrogen distribution of no less than 1 e22 atcm3 as peak value, for a total amount of no less than 1e15 atcm2.
13. The process of claim 12, wherein the barrier layer includes silicon nitride oxide having a thickness between 0.5 to 5.0 nm.
14. The process of claim 12, wherein the interlevel dielectric layer is formed after forming the barrier layer.
15. The process of claim 12, further comprising etching the first conductive layer to form the floating gate region of the memory cell immediately before forming the barrier layer.
16. The process of claim 12, further comprising defining the first conductive layer to form a floating gate region of the memory cell immediately after forming the barrier layer.
17. The process of claim 12, wherein the interlevel dielectric layer includes a triple ONO layer formed by CVD.
18. The process of claim 12, wherein the interpoly dielectric includes only a single layer of silicon oxide formed by CVD.
19. A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising:
forming source and drain regions in a semiconductor substrate;
forming a thin dielectric layer on the semiconductor substrate;
forming a first conductive layer on said thin dielectric layer;
directly nitriding a top surface of the first conductive layer, using radical nitrogen, thereby forming a barrier layer directly above and contacting a top surface of a floating gate region of the first conductive layer;
depositing an interlevel dielectric layer directly on a top surface of the barrier layer formed by directly nitriding the top surface of the first conductive layer, whereby the barrier layer intervenes between the interlevel dielectric layer and the floating gate region such that no portion of the floating gate region contacts the interlevel dielectric layer; and
forming a second conductive layer on the interlevel dielectric layer;
wherein the barrier layer includes silicon nitride oxide having a nitrogen distribution of no less than 1e22 atcm3 as peak value, for a total amount of no less than 1e15 atcm3.
20. The process of claim 19, wherein the barrier layer includes silicon nitride oxide having a thickness between 0.5 to 5.0 nm.
21. The process of claim 19, wherein the interlevel dielectric layer is formed after forming the barrier layer.
22. The process of claim 19, further comprising etching the first conductive layer to form the floating gate region immediately before forming the barrier layer.
23. The process of claim 19, wherein the interlevel dielectric layer includes a triple ONO layer formed by CVD.
24. The process of claim 19 wherein directly nitriding the top surface of the first conductive layer includes directly nitriding the top surface of the first conductive layer in a manner that leaves the barrier layer covering the entire top surface of the floating gate region.
25. The process of claim 12 wherein forming an interlevel dielectric layer includes depositing an oxide layer directly on the barrier layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A magnetic recording apparatus comprising:
a composite magnetic head which includes a recording head and a reproducing head; and
a magnetic storage medium in which data is recorded, including,
a discrete area, having a plurality of tracks and a non-magnetic area between adjacent tracks, the tracks having a magnetic recording area where data can be written by the recording head, the data not being able to be written in the non-magnetic area by the recording head in the non-magnetic area,
a correction information recording area, positioning correction information being able to be written in the correction information recording area used for positioning either the recording head or the reproducing head at each track center, and
a center shift amount detection area, center shift amount detection information being previously recorded in the center shift amount detection area, the center shift amount detection information being for measuring a center shift amount which indicates a relative distance between a tracking center and an actual track center of the discrete area when either the recording head or the reproducing head is positioned at a track center.
2. The magnetic recording apparatus according to claim 1, wherein the center shift amount detection area is provided in the discrete area.
3. The magnetic recording apparatus according to claim 1, wherein the correction information recording area is provided over a radial direction of the magnetic storage medium.
4. The magnetic recording apparatus according to claim 3, wherein the magnetic storage medium further includes a servo area in which position information for positioning the composite magnetic head is recorded, and
the correction information recording area is provided between the servo area and the discrete area.
5. The magnetic recording apparatus according to claim 4, wherein the servo area includes
a preamble portion in which information for synchronizing a clock of a reproduction signal is recorded;
an address portion in which information on a cylinder is recorded; and
a deviation detection portion in which detection information for detecting an off-track amount of the composite magnetic head is recorded.
6. The magnetic recording apparatus according to claim 5, wherein the detection information in the deviation detection portion is recorded with a pattern oblique to an information recording pattern of the preamble portion.
7. The magnetic recording apparatus according to claim 6, wherein the correction information recording area and the center shift amount detection area are provided in each sector area constituting the track.
8. The magnetic recording apparatus according to claim 1, wherein the center shift amount detection information is recorded in the center shift amount recording area while phases in the radial direction of an odd-number track and an even-number track are shifted from each other by 180 degrees.
9. The magnetic recording apparatus according to claim 1, wherein the positioning correction information is recorded in the correction information recording area, the positioning correction information having first correction information for positioning the reproducing head at each track center position.
10. The magnetic recording apparatus according to claim 9, wherein the positioning correction information has second correction information for positioning the recording head at each track center position.
11. The magnetic recording apparatus according to claim 10, wherein the second correction information includes an offset amount indicating a relative distance in a radial direction between the reproducing head and the recording head.
12. The magnetic recording apparatus according to claim 10, further comprising:
a reproduction unit which reads the center shift amount detection information with the reproducing head while the reproducing head is moved by a predetermined distance in the radial direction from a position where the reproducing head is positioned at a predetermined track; and
a determination unit which determines the positioning correction information based on the center shift amount detection information which is read a plurality of times by moving the reproducing head and the recording head.
13. The magnetic recording apparatus according to claim 12, wherein the positioning correction information is recorded in the correction information recording area of a sector immediately before a sector where the positioning correction information is determined by the determination unit.
14. The magnetic recording apparatus according to claim 12, wherein an average value of pieces of the positioning correction information determined in the tracks within a predetermined area is recorded in the correction information recording area in the form of the common positioning correction information in the predetermined area.
15. A positioning correction method comprising:
reading center shift amount detection information with a reproducing head while a reproducing head is moved by a predetermined distance in a radial direction from a position where the reproducing head is positioned at a predetermined track in a discrete track type magnetic storage medium, the discrete track type magnetic storage medium including a discrete area, a correction information recording area, and a center shift amount detection area, the discrete area having a plurality of tracks and a non-magnetic area between the adjacent tracks, the track having a magnetic recording area where data can be written by the recording head, the data not being able to be written in the non-magnetic area by the recording head in the non-magnetic area, positioning correction information being able to be written in the correction information recording area when either the recording head or the reproducing head is positioned at each track center, center shift amount detection information being previously recorded in the center shift amount detection area, the center shift amount detection information for measuring a center shift amount which is of a relative distance between a tracking center and an actual track center of the discrete area when either the recording head or the reproducing head is positioned at each track center; and
moving the reproducing head and the recording head and reading the center shift amount detection information a plurality of times, and determining the positioning correction information based on the center shift amount detection information read.