1. A method of arranging a plurality of sensor elements to form a sensor array, comprising:
arranging the plurality of elements to form two or more sub-rows along an axis;
wherein the elements in a first of the two or more sub-rows are positioned in a staggered arrangement with the elements in a second of the two or more sub-rows.
2. The method of claim 1, wherein groups of corresponding elements form columns of the sensor element array.
3. The method of claim 1, wherein output data from the first of the two or more sub-row elements is combined with output data from the second of the two or more sub-row elements to form a data frame.
4. The method of claim 3, wherein the data frame is representative of segments of a biological surface along the axis.
5. The method of claim 4, wherein the surface is at least one of a fingerprint and a palm-print.
6. The method of claim 4, wherein the segments are substantially continuous along the axis.
7. The method of claim 4, wherein a distance between the segments is substantially zero.
8. The method of claim 4, wherein a rate of the combining is a function of at least one of speed and acceleration of movement of the biological surface across the array.
9. A sensor array, comprising:
a plurality of sensor elements combined to form two or more sub-rows along an axis of the array;
wherein the elements in a first of the two or more sub-rows are positioned in a staggered arrangement with the elements in a second of the two or more sub-rows.
10. The sensor array of claim 9, wherein groups of corresponding elements form columns of the sensor element array.
11. The sensor array of claim 9, wherein output data from the first of the two or more sub-row elements is configured to be combined with output data from the second of the two or more sub-row elements to form a data frame.
12. The sensor array of claim 11, wherein the data frame is representative of segments of a biological surface along the axis.
13. The sensor array of claim 12, wherein the surface is at least one of a fingerprint and a palm-print.
14. The sensor array of claim 12, wherein the segments are substantially continuous along the axis.
15. The sensor array of claim 12, wherein a distance between the segments is substantially zero.
16. The sensor array of claim 11, wherein a rate of the combining is a function of at least one of speed and acceleration of movement of the biological surface across the array.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit (\u201cIC\u201d) package, comprising:
a plurality of inputoutput (\u201cIO\u201d) pins;
at least one no-connect (\u201cNC\u201d) pin;
a resident IC configured to process data;
an IO buffer circuit having a plurality of data paths, each data path providing a data connection between and IO node of the resident IC and a corresponding IO pin; and
a spare IO buffer circuit having:
a pin selection circuit configured to generate a pin selection signal associated with a data path of the IO buffer circuit, the pin selection circuit including a memory configured to store the address of a data path of the IO circuit to be replaced, and a demultiplexer circuit coupled with the memory and configured to provide the pin selection signal to at least one of the multiplexer circuits of the IO path converter circuit being associated with a data path to be replaced, and
an IO path converter circuit configured to couple an IO node of the resident IC with the NC pin in response to the pin selection signal, the IO path converter circuit including a multiplexer circuit associated each with data path of the IO circuit, the multiplexer circuit having a first input coupled with the NC pin, a second input coupled with the associated data path of the IO circuit, and an output coupled with the associated an IO node of the resident IC, wherein the multiplexer circuit couples the NC pin to the IO node in response to the pin selection signal.
2. The integrated circuit package of claim 1, wherein the IO circuit comprises:
an IO protection circuit coupled to the IO pins; and
a data buffer coupled to the IO protection circuit and configured to provide a temporary buffer for the resident IC.
3. An integrated circuit (\u201cIC\u201d) package, comprising:
a plurality of inputoutput (\u201cIO\u201d) pins;
at least one no-connect (\u201cNC\u201d) pin;
a resident IC configured to process data;
an IO protection circuit coupled to the IO pins;
a data buffer coupled to the IO protection circuit and configured to provide a temporary buffer for the resident IC;
an IO buffer circuit configured to couple the plurality of IO pins with the resident IC, wherein the IO buffer circuit includes a plurality of data paths, each data path providing a data connection between an IO node of the resident IC and a corresponding IO pin; and
a spare IO buffer circuit configured to selectively provide a data path between the NC pin and the resident IC, the spare IO buffer including:
a pin selection circuit configured to generate a pin selection signal associated with a data path of the IO buffer circuit, the pin selection circuit including a memory configured to store the address of a data path of the IO circuit to be replaced, and a demultiplexer circuit coupled with the memory and configured to provide the pin selection signal to at least one of the multiplexer circuits of the IO path converter circuit being associated with a data path to be replaced, and
an IO path converter circuit configured to couple an IO node of the resident IC with the NC pin in response to the pin selection signal, the IO path converter circuit including a multiplexer circuit associated each with data path of the IO circuit, each multiplexer circuit having a first input coupled with the NC pin, a second input coupled with the associated data path of the IO circuit, and an output coupled with the associated an IO node of the resident IC, wherein the multiplexer circuit couples the NC pin to the IO node in response to the pin selection signal.
4. The integrated circuit package of claim 3, wherein the pin selection circuit comprises a plurality of electronic fuses, each electronic fuse being associated with a multiplexer of the IO path converter circuit and configured to couple the associated multiplexer to the pin selection signal.
5. An integrated circuit (\u201cIC\u201d) package, comprising:
a plurality of inputoutput (\u201cIO\u201d) pins;
at least one no-connect (\u201cNC\u201d) pin;
a resident IC configured to process data;
an IO protection circuit coupled to the IO pins;
a data buffer coupled to the IO protection circuit and configured to provide a temporary buffer for the resident IC;
an IO buffer circuit configured to couple the plurality of IO pins with the resident IC, wherein the IO buffer circuit includes a plurality of data paths, each data path providing a data connection between an IO node of the resident IC and a corresponding IO pin; and
a spare IO buffer circuit configured to selectively provide a data path between the NC pin and the resident IC, the spare IO buffer including:
a pin selection circuit configured to generate a pin selection signal associated with a data path of the IO buffer circuit, and includes a decoder configured to generate the pin selection, and
an IO path converter circuit configured to couple an IO node of the resident IC with the NC pin in response to the pin selection signal, the IO path converter circuit including a multiplexer circuit associated each with data path of the IO circuit, each multiplexer circuit having a first input coupled with the NC pin, a second input coupled with the associated data path of the IO circuit, and an output coupled with the associated an IO node of the resident IC, wherein the multiplexer circuit couples the NC pin to the IO node in response to the pin selection signal.
6. The integrated circuit package of claim 2, wherein the protection circuit comprises voltage surge protection.
7. The integrated circuit package of claim 2, wherein the protection circuit comprising current surge protection.
8. An integrated circuit (\u201cIC\u201d) package, comprising:
a plurality of pins including a plurality of inputoutput (\u201cIO\u201d) pins and at least one no-connection (\u201cNC\u201d) pin;
a resident IC configured to process data;
an IO buffer circuit having a plurality of data paths, each data path providing a data connection between at least one of the plurality of IO pins and an associated IO node of the resident IC; and
a spare IO buffer circuit having a pin selection circuit including a decoder configured to generate a pin selection signal associated with a data path of the spare IO buffer circuit, and an IO path converter circuit configured to couple an IO node of the resident IC and at least one of the NC pins in response to the pin selection signal, and wherein the IO path converter circuit includes a multiplexer circuit associated each with data path of the IO circuit, the multiplexer circuit comprising, a first input coupled with the NC pin; a second input coupled with the associated data path of the IO circuit; and an output coupled with the associated an IO node of the resident IC, wherein the multiplexer circuit couples the NC pin to the IO node in response to the pin selection signal.
9. The integrated circuit package of claim 8, wherein the pin selection circuit comprises a plurality of electronic fuses, each electronic fuse being associated with a multiplexer of the IO path converter circuit and configured to couple the associated multiplexer to the pin selection signal.
10. The integrated circuit package of claim 8, wherein the IO circuit comprises:
an IO protection circuit coupled to the IO pins; and
a data buffer coupled to the IO protection circuit and configured to provide a temporary buffer for the resident IC.
11. The integrated circuit package of claim 10, wherein the IO protection circuit comprises voltage surge protection.
12. The integrated circuit package of claim 10, wherein the IO protection circuit comprises current surge protection.