1. Device for detecting and indicating at least one environment parameter, comprising transducer means suitable for detecting said at least one parameter detected at said environment and for producing at least one electrical signal in output proportional to it as well as indicator means, wherein said transducer means cooperate with digitising means of said at least one signal and at least one comparating unit suitable for comparing said at least one digital signal with at least one preset reference value to generate a command signal to said indicator means, said indicator means being of the optical type and representing the state of normality, alarm or danger of the level of said parameter detected at said environment.
2. Device according to claim 1, wherein said transducer means comprises at least one amplifier of the detected signal, arranged upstream of said digitising means, suitable for guaranteeing the reliability of the interpretation and transmission of said signal.
3. Device according to claim 1, wherein said indicator means, are of the traffic light type, usually associated with alarm andor danger.
4. Device according to claim 3, wherein said traffic light type indicators comprise three lights in colours green, yellow and red, with which three noise levels inside said room are associated, representing normality, warning and danger respectively.
5. Device, according to claim 1, wherein it also comprises an electronic processing system for storingrecording, even for many years, the levels reached by said parameter detected by said transducer means.
6. Device according to claim 5, wherein said electronic processing system comprises means for filing said levels.
7. Device according to claim 6, wherein said filing means comprises at least one consultable memory unit suitable for containing said detected levels indefinitely.
8. Device according to claim 5, wherein said electronic processing system is equipped with at least one monitor suitable for graphically visualising directly or after suitable processing, said stored values, as well as their variations in a predetermined time period.
9. Device according to claim 5, wherein said processing system comprises at least one printing unit suitable for printing, directly or after suitable processing, said stored values as well as their variations in a predetermined time period.
10. Device according to claim 1, wherein said transducer means comprises at least one electroacoustic transducer suitable for detecting the acoustic pressure existing.
11. Device according to claim 1, wherein said transducer means comprises at least one transducer, suitable for detecting the humidity.
12. Device according to claim 1, wherein said transducer means comprises at least one transducer suitable for detecting the temperature.
13. Device according to claim 1, wherein said transducer means comprises at least one transducer suitable for detecting the electromagnetic pollution.
14. Device according to claim 1, wherein said transducer means comprises at least one transducer suitable for detecting the dusts.
15. Device, according to claim 1, wherein the amplifier and digitiser devices are fed by the mains.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A shift register unit, comprising:
an input module connected to a first input signal terminal, a first direct current signal terminal, a second input signal terminal and a second direct current signal terminal respectively, and configured to provide a first input signal received by the first input signal terminal to a pulling-up node according to a first direct current signal received by the first direct current signal terminal, and provide a second input signal received by the second input signal terminal to the pulling-up node according to a second direct current signal received by the second direct current signal terminal;
an output module connected to a first clock signal terminal and configured to provide a first clock signal received by the first clock signal terminal to an output terminal according to a voltage signal of the pulling-up node;
a pulling-down driving module connected to the first clock signal terminal, a second clock signal terminal and a low voltage signal terminal, and configured to provide a second clock signal received by the second clock signal terminal to a pulling-down node according to the first clock signal received by the first clock signal terminal and the second clock signal, and provide a low voltage signal received by the low voltage signal terminal to the pulling-down node according to the voltage signal of the pulling-up node;
a pulling-down module connected to the low voltage signal terminal, and configured to provide the low voltage signal received by the low voltage signal terminal to the pulling-up node and the output terminal according to the voltage signal of the pulling-down node;
a resetting module connected to the second clock signal terminal and the low voltage signal terminal respectively, and configured to provide the low voltage signal received by the low voltage signal terminal to the output terminal according to the second clock signal received by the second clock signal terminal,
wherein the pulling-up node is a connecting point of the input module and the output module, and the pulling-down driving module is connected to the pulling-down module through the pulling-down node.
2. The shift register unit according to claim 1, wherein the input module comprises a first transistor, a second transistor, a third transistor and a fourth transistor;
a gate and a source of the first transistor are connected to the first input signal terminal;
a drain of the second transistor is connected to a drain of the first transistor, a gate thereof is connected to the first direct current signal terminal, and a source thereof is connected to the pulling-up node;
a gate and a source of the third transistor are connected to the second input signal terminal, and a drain thereof is connected to the pulling-up node; and
a source of the fourth transistor is connected to the drain of the third transistor, a gate thereof is connected to the second direct current signal terminal, and a drain thereof is connected to the pulling-up node.
3. The shift register unit according to claim 2, wherein the output module comprises a fifth transistor and a first capacitor;
a gate of the fifth transistor is connected to the pulling-up node, a drain thereof is connected to the first clock signal terminal, and a source thereof is connected to the output terminal; and
one terminal of the first capacitor is connected to the pulling-up node, and another terminal of the first capacitor is connected to the low voltage signal terminal or the output terminal.
4. The shift register unit according to claim 3, wherein the pulling-down driving module comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor;
a gate and a drain of the seventh transistor are connected to the first clock signal terminal, and a source thereof connected to a gate of the ninth transistor;
a drain of the ninth transistor is connected to the second clock signal terminal, and a source thereof is connected to a source of the eighth transistor;
a gate of the eighth transistor is connected to the second clock signal terminal, and the drain thereof is connected to the pulling-down node;
a gate of the sixth transistor is connected to the pulling-up node, a drain thereof is connected to the pulling-down node, and a source thereof is connected to the low voltage signal terminal; and
one terminal of the second capacitor is connected to the low voltage signal terminal, and another terminal thereof is connected to the source of the seventh transistor.
5. The shift register unit according to claim 4, wherein the pulling-down module comprises a tenth transistor and an eleventh transistor;
a drain of the tenth transistor is connected to the low voltage signal terminal, a source thereof is connected to the pulling-up node, and a gate thereof is connected to the pulling-down node; and
a gate of the eleventh transistor is connected to the pulling-down node, a source thereof is connected to the low voltage signal terminal, and a drain thereof is connected to the output terminal.
6. The shift register unit according to claim 5, wherein the resetting unit comprises a twelfth transistor;
a gate of the twelfth transistor is connected to the second clock signal terminal, a drain thereof is connected to the low voltage signal terminal, and a source thereof is connected to the output terminal.
7. The shift register unit according to claim 1, wherein the first direct current signal has a phase opposite to that of the second direct current signal.
8. The shift register unit according to claim 1, wherein the first dock signal has a phase opposite to that of the second clock signal.
9. A gate driving circuit comprising multiple stages of shift register units according to claim 1; except for a first stage of shift register unit and a last stage of shift register unit, a first input signal of each stage of shift register is connected to an output terminal of an adjacent previous stage of shift register unit, a second input signal of each sage of shift register unit is connected to an output terminal of an adjacent next shift register unit, and an output terminal of each stage of shift register unit is connected to a second input signal terminal of the adjacent previous stage of shift register unit and a first input signal terminal of the adjacent next stage of shift register unit.
10. A display device comprising the gate driving circuit according to claim 9.
11. The gate driving circuit according to claim 9, wherein the input module comprises a first transistor, a second transistor, a third transistor and a fourth transistor;
a gate and a source of the first transistor are connected to the first input signal terminal;
a drain of the second transistor is connected to a drain of the first transistor, a gate thereof is connected to the first direct current signal terminal, and a source thereof is connected to the pulling-up node;
a gate and a source of the third transistor are connected to the second input signal terminal, and a drain thereof is connected to the pulling-up node; and
a source of the fourth transistor is connected to the drain of the third transistor, a gate thereof is connected to the second direct current signal terminal, and a drain thereof is connected to the pulling-up node.
11. The gate driving circuit according to claim 11, wherein the output module comprises a fifth transistor and a first capacitor;
a gate of the fifth transistor is connected to the pulling-up node, a drain thereof is connected to the first clock signal terminal, and a source thereof is connected to the output terminal; and
one terminal of the first capacitor is connected to the pulling-up node, and another terminal of the first capacitor is connected to the low voltage signal terminal or the output terminal.
13. The gate driving circuit according to claim 12, wherein the pulling-down driving module comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor;
a gate and a drain of the seventh transistor are connected to the first clock signal terminal, and a source thereof connected to a gate of the ninth transistor;
a drain of the ninth transistor is connected to the second clock signal terminal, and a source thereof is connected to a source of the eighth transistor;
a gate of the eighth transistor is connected to the second clock signal terminal, and the drain thereof is connected to the pulling-down node;
a gate of the sixth transistor is connected to the pulling-up node, a drain thereof is connected to the pulling-down node, and a source thereof is connected to the low voltage signal terminal; and
one terminal of the second capacitor is connected to the low voltage signal terminal, and another terminal thereof is connected to the source of the seventh transistor.
14. The gate driving circuit according to claim 13, wherein the pulling-down module comprises a tenth transistor and an eleventh transistor;
a drain of the tenth transistor is connected to the low voltage signal terminal, a source thereof is connected to the pulling-up node, and a gate thereof is connected to the pulling-down node; and
a gate of the eleventh transistor is connected to the pulling-down node, a source thereof is connected to the low voltage signal terminal, and a drain thereof is connected to the output terminal.
15. The gate driving circuit according to claim 14, wherein the resetting unit comprises a twelfth transistor;
a gate of the twelfth transistor is connected to the second clock signal terminal, a drain thereof is connected to the low voltage signal terminal, and a source thereof is connected to the output terminal.
16. The display device according to claim 10, wherein the input module comprises a first transistor, a second transistor, a third transistor and a fourth transistor;
a gate and a source of the first transistor are connected to the first input signal terminal;
a drain of the second transistor is connected to a drain of the first transistor, a gate thereof is connected to the first direct current signal terminal, and a source thereof is connected to the pulling-up node;
a gate and a source of the third transistor are connected to the second input signal terminal, and a drain thereof is connected to the pulling-up node; and
a source of the fourth transistor is connected to the drain of the third transistor, a gate thereof is connected to the second direct current signal terminal, and a drain thereof is connected to the pulling-up node.
17. The display device according to claim 16, wherein the output module comprises a fifth transistor and a first capacitor;
a gate of the fifth transistor is connected to the pulling-up node, a drain thereof is connected to the first clock signal terminal, and a source thereof is connected to the output terminal; and
one terminal of the first capacitor is connected to the pulling-up node, and another terminal of the first capacitor is connected to the low voltage signal terminal or the output terminal.
18. The display device according to claim 17, wherein the pulling-down driving module comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor;
a gate and a drain of the seventh transistor are connected to the first clock signal terminal, and a source thereof connected to a gate of the ninth transistor;
a drain of the ninth transistor is connected to the second clock signal terminal, and a source thereof is connected to a source of the eighth transistor;
a gate of the eighth transistor is connected to the second clock signal terminal, and the drain thereof is connected to the pulling-down node;
a gate of the sixth transistor is connected to the pulling-up node, a drain thereof is connected to the pulling-down node, and a source thereof is connected to the low voltage signal terminal; and
one terminal of the second capacitor is connected to the low voltage signal terminal, and another terminal thereof is connected to the source of the seventh transistor.
19. The display device according to claim 1$, wherein the pulling-down module comprises a tenth transistor and an eleventh transistor;
a drain of the tenth transistor is connected to the low voltage signal terminal, a source thereof is connected to the pulling-up node, and a gate thereof is connected to the pulling-down node; and
a gate of the eleventh transistor is connected to the pulling-down node, a source thereof is connected to the low voltage signal terminal, and a drain thereof is connected to the output terminal.
20. The display device according to claim 19, wherein the resetting unit comprises a twelfth transistor;
a gate of the twelfth transistor is connected to the second clock signal terminal, a drain thereof is connected to the low voltage signal terminal, and a source thereof is connected to the output terminal.